From: Eric Anholt <eric@anholt.net> To: dri-devel@lists.freedesktop.org Cc: linux-kernel@vger.kernel.org, Dave Emett <david.emett@broadcom.com>, Thomas Spurden <thomas.spurden@broadcom.com>, Eric Anholt <eric@anholt.net> Subject: [PATCH v2 1/6] drm/v3d: Document cache flushing ABI. Date: Mon, 3 Dec 2018 14:24:33 -0800 [thread overview] Message-ID: <20181203222438.25417-1-eric@anholt.net> (raw) Right now, userspace doesn't do any L2T writes, but we should lay out our expectations for how it works. v2: Explicitly mention the VCD cache flushing requirements and that we'll flush the other caches before each of the CLs. Signed-off-by: Eric Anholt <eric@anholt.net> --- include/uapi/drm/v3d_drm.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/uapi/drm/v3d_drm.h b/include/uapi/drm/v3d_drm.h index 35c7d813c66e..ea70669d2138 100644 --- a/include/uapi/drm/v3d_drm.h +++ b/include/uapi/drm/v3d_drm.h @@ -52,6 +52,14 @@ extern "C" { * * This asks the kernel to have the GPU execute an optional binner * command list, and a render command list. + * + * The L1T, slice, L2C, L2T, and GCA caches will be flushed before + * each CL executes. The VCD cache should be flushed (if necessary) + * by the submitted CLs. The TLB writes are guaranteed to have been + * flushed by the time the render done IRQ happens, which is the + * trigger for out_sync. Any dirtying of cachelines by the job (only + * possible using TMU writes) must be flushed by the caller using the + * CL's cache flush commands. */ struct drm_v3d_submit_cl { /* Pointer to the binner command list. -- 2.20.0.rc1
WARNING: multiple messages have this Message-ID (diff)
From: Eric Anholt <eric@anholt.net> To: dri-devel@lists.freedesktop.org Cc: Dave Emett <david.emett@broadcom.com>, Thomas Spurden <thomas.spurden@broadcom.com>, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/6] drm/v3d: Document cache flushing ABI. Date: Mon, 3 Dec 2018 14:24:33 -0800 [thread overview] Message-ID: <20181203222438.25417-1-eric@anholt.net> (raw) Right now, userspace doesn't do any L2T writes, but we should lay out our expectations for how it works. v2: Explicitly mention the VCD cache flushing requirements and that we'll flush the other caches before each of the CLs. Signed-off-by: Eric Anholt <eric@anholt.net> --- include/uapi/drm/v3d_drm.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/uapi/drm/v3d_drm.h b/include/uapi/drm/v3d_drm.h index 35c7d813c66e..ea70669d2138 100644 --- a/include/uapi/drm/v3d_drm.h +++ b/include/uapi/drm/v3d_drm.h @@ -52,6 +52,14 @@ extern "C" { * * This asks the kernel to have the GPU execute an optional binner * command list, and a render command list. + * + * The L1T, slice, L2C, L2T, and GCA caches will be flushed before + * each CL executes. The VCD cache should be flushed (if necessary) + * by the submitted CLs. The TLB writes are guaranteed to have been + * flushed by the time the render done IRQ happens, which is the + * trigger for out_sync. Any dirtying of cachelines by the job (only + * possible using TMU writes) must be flushed by the caller using the + * CL's cache flush commands. */ struct drm_v3d_submit_cl { /* Pointer to the binner command list. -- 2.20.0.rc1 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
next reply other threads:[~2018-12-03 22:24 UTC|newest] Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-12-03 22:24 Eric Anholt [this message] 2018-12-03 22:24 ` [PATCH v2 1/6] drm/v3d: Document cache flushing ABI Eric Anholt 2018-12-03 22:24 ` [PATCH v2 2/6] drm/v3d: Drop unused v3d_flush_caches() Eric Anholt 2018-12-03 22:24 ` Eric Anholt 2018-12-03 22:24 ` [PATCH v2 3/6] drm/v3d: Don't bother flushing L1TD at job start Eric Anholt 2018-12-03 22:24 ` [PATCH v2 4/6] drm/v3d: Drop the wait for L2T flush to complete Eric Anholt 2018-12-03 22:24 ` Eric Anholt 2018-12-04 11:53 ` Dave Emett 2018-12-03 22:24 ` [PATCH v2 5/6] drm/v3d: Stop trying to flush L2C on V3D 3.3+ Eric Anholt 2018-12-04 11:54 ` Dave Emett 2018-12-03 22:24 ` [PATCH v2 6/6] drm/v3d: Invalidate the caches from the outside in Eric Anholt 2018-12-04 12:01 ` Dave Emett 2018-12-04 11:51 ` [PATCH v2 1/6] drm/v3d: Document cache flushing ABI Dave Emett
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