From: Paul Walmsley <paul.walmsley@sifive.com> To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Paul Walmsley <paul.walmsley@sifive.com>, Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Palmer Dabbelt <palmer@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, devicetree@vger.kernel.org, Paul Walmsley <paul@pwsan.com> Subject: [PATCH 5/7] riscv: dts: add initial support for the SiFive FU540-C000 SoC Date: Fri, 14 Dec 2018 21:21:52 -0800 [thread overview] Message-ID: <20181215052154.24347-6-paul.walmsley@sifive.com> (raw) In-Reply-To: <20181215052154.24347-1-paul.walmsley@sifive.com> Add initial support for the SiFive FU540-C000 SoC. This is a 28nm SoC based around the SiFive U54-MC core complex and a TileLink interconnect. This file is expected to grow considerably as more device drivers are added to the kernel. Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: devicetree@vger.kernel.org Cc: linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> --- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 182 +++++++++++++++++++++ 1 file changed, 182 insertions(+) create mode 100644 arch/riscv/boot/dts/sifive/fu540-c000.dtsi diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi new file mode 100644 index 000000000000..0ef314cf17b6 --- /dev/null +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-License-Identifier: GPL-2.0-or-later +/* Copyright (c) 2018 SiFive, Inc */ +/* See the file LICENSE for further information */ + +/dts-v1/; + +#include <linux/clk/sifive-fu540-prci.h> + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540-c000", "sifive,fu540"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <1000000>; + cpu0: cpu@0 { + clock-frequency = <0>; + compatible = "sifive,e51", "sifive,rocket0"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + reg = <0>; + riscv,isa = "rv64imac"; + status = "okay"; + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu1: cpu@1 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <1>; + riscv,isa = "rv64imafdc"; + status = "okay"; + tlb-split; + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu2: cpu@2 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <2>; + riscv,isa = "rv64imafdc"; + status = "okay"; + tlb-split; + cpu2_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu3: cpu@3 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <3>; + riscv,isa = "rv64imafdc"; + status = "okay"; + tlb-split; + cpu3_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu4: cpu@4 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <4>; + riscv,isa = "rv64imafdc"; + status = "okay"; + tlb-split; + cpu4_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus"; + ranges; + prci: prci@10000000 { + compatible = "sifive,fu540-c000-prci"; + reg = <0x0 0x10000000 0x0 0x1000>; + clocks = <&hfclk>, <&rtcclk>; + #clock-cells = <1>; + }; + uart0: serial@10010000 { + compatible = "sifive,fu540-c000-uart", "sifive,uart0"; + interrupt-parent = <&plic0>; + interrupts = <4>; + reg = <0x0 0x10010000 0x0 0x1000>; + clocks = <&prci PRCI_CLK_TLCLK>; + }; + uart1: serial@10011000 { + compatible = "sifive,fu540-c000-uart", "sifive,uart0"; + interrupt-parent = <&plic0>; + interrupts = <5>; + reg = <0x0 0x10011000 0x0 0x1000>; + clocks = <&prci PRCI_CLK_TLCLK>; + }; + plic0: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = < + &cpu0_intc 11 + &cpu1_intc 11 &cpu1_intc 9 + &cpu2_intc 11 &cpu2_intc 9 + &cpu3_intc 11 &cpu3_intc 9 + &cpu4_intc 11 &cpu4_intc 9>; + reg = <0x0 0xc000000 0x0 0x4000000>; + }; + }; +}; -- 2.20.0
WARNING: multiple messages have this Message-ID (diff)
From: Paul Walmsley <paul.walmsley@sifive.com> To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Mark Rutland <mark.rutland@arm.com>, devicetree@vger.kernel.org, Paul Walmsley <paul@pwsan.com>, Albert Ou <aou@eecs.berkeley.edu>, Palmer Dabbelt <palmer@sifive.com>, Rob Herring <robh+dt@kernel.org>, Paul Walmsley <paul.walmsley@sifive.com> Subject: [PATCH 5/7] riscv: dts: add initial support for the SiFive FU540-C000 SoC Date: Fri, 14 Dec 2018 21:21:52 -0800 [thread overview] Message-ID: <20181215052154.24347-6-paul.walmsley@sifive.com> (raw) In-Reply-To: <20181215052154.24347-1-paul.walmsley@sifive.com> Add initial support for the SiFive FU540-C000 SoC. This is a 28nm SoC based around the SiFive U54-MC core complex and a TileLink interconnect. This file is expected to grow considerably as more device drivers are added to the kernel. Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: devicetree@vger.kernel.org Cc: linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> --- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 182 +++++++++++++++++++++ 1 file changed, 182 insertions(+) create mode 100644 arch/riscv/boot/dts/sifive/fu540-c000.dtsi diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi new file mode 100644 index 000000000000..0ef314cf17b6 --- /dev/null +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-License-Identifier: GPL-2.0-or-later +/* Copyright (c) 2018 SiFive, Inc */ +/* See the file LICENSE for further information */ + +/dts-v1/; + +#include <linux/clk/sifive-fu540-prci.h> + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540-c000", "sifive,fu540"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <1000000>; + cpu0: cpu@0 { + clock-frequency = <0>; + compatible = "sifive,e51", "sifive,rocket0"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + reg = <0>; + riscv,isa = "rv64imac"; + status = "okay"; + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu1: cpu@1 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <1>; + riscv,isa = "rv64imafdc"; + status = "okay"; + tlb-split; + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu2: cpu@2 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <2>; + riscv,isa = "rv64imafdc"; + status = "okay"; + tlb-split; + cpu2_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu3: cpu@3 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <3>; + riscv,isa = "rv64imafdc"; + status = "okay"; + tlb-split; + cpu3_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu4: cpu@4 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <4>; + riscv,isa = "rv64imafdc"; + status = "okay"; + tlb-split; + cpu4_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus"; + ranges; + prci: prci@10000000 { + compatible = "sifive,fu540-c000-prci"; + reg = <0x0 0x10000000 0x0 0x1000>; + clocks = <&hfclk>, <&rtcclk>; + #clock-cells = <1>; + }; + uart0: serial@10010000 { + compatible = "sifive,fu540-c000-uart", "sifive,uart0"; + interrupt-parent = <&plic0>; + interrupts = <4>; + reg = <0x0 0x10010000 0x0 0x1000>; + clocks = <&prci PRCI_CLK_TLCLK>; + }; + uart1: serial@10011000 { + compatible = "sifive,fu540-c000-uart", "sifive,uart0"; + interrupt-parent = <&plic0>; + interrupts = <5>; + reg = <0x0 0x10011000 0x0 0x1000>; + clocks = <&prci PRCI_CLK_TLCLK>; + }; + plic0: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = < + &cpu0_intc 11 + &cpu1_intc 11 &cpu1_intc 9 + &cpu2_intc 11 &cpu2_intc 9 + &cpu3_intc 11 &cpu3_intc 9 + &cpu4_intc 11 &cpu4_intc 9>; + reg = <0x0 0xc000000 0x0 0x4000000>; + }; + }; +}; -- 2.20.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2018-12-15 5:22 UTC|newest] Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-12-15 5:21 [PATCH 0/7] arch: riscv: add DT file support, starting with the SiFive HiFive-U Paul Walmsley 2018-12-15 5:21 ` Paul Walmsley 2018-12-15 5:21 ` [PATCH 1/7] arch: riscv: add support for building DTB files from DT source data Paul Walmsley 2018-12-15 5:21 ` Paul Walmsley 2018-12-15 5:21 ` [PATCH 2/7] dt-bindings: riscv: sifive: add documentation for the SiFive FU540 Paul Walmsley 2018-12-15 5:21 ` Paul Walmsley 2018-12-20 20:57 ` Rob Herring 2018-12-20 20:57 ` Rob Herring 2018-12-15 5:21 ` [PATCH 3/7] dt-bindings: riscv: cpus: add E51 cores to the list of documented CPUs Paul Walmsley 2018-12-15 5:21 ` Paul Walmsley 2018-12-15 5:21 ` Paul Walmsley 2018-12-20 21:01 ` Rob Herring 2018-12-20 21:01 ` Rob Herring 2019-01-04 22:46 ` Palmer Dabbelt 2019-01-04 22:46 ` Palmer Dabbelt 2019-01-05 1:10 ` Rob Herring 2019-01-05 1:10 ` Rob Herring 2018-12-15 5:21 ` [PATCH 4/7] dt-bindings: riscv: cpus: add U54 " Paul Walmsley 2018-12-15 5:21 ` Paul Walmsley 2018-12-15 5:21 ` Paul Walmsley [this message] 2018-12-15 5:21 ` [PATCH 5/7] riscv: dts: add initial support for the SiFive FU540-C000 SoC Paul Walmsley 2018-12-16 3:12 ` kbuild test robot 2018-12-16 3:12 ` kbuild test robot 2018-12-16 3:12 ` kbuild test robot 2019-01-21 14:10 ` Johan Hovold 2019-01-21 14:10 ` Johan Hovold 2019-01-21 14:10 ` Johan Hovold 2018-12-15 5:21 ` [PATCH 6/7] dt-binding: riscv: sifive: add documentation for FU540-based boards Paul Walmsley 2018-12-15 5:21 ` Paul Walmsley 2018-12-20 21:04 ` Rob Herring 2018-12-20 21:04 ` Rob Herring 2018-12-20 21:04 ` Rob Herring 2018-12-15 5:21 ` [PATCH 7/7] riscv: dts: add initial board data for the SiFive HiFive Unleashed Paul Walmsley 2018-12-15 5:21 ` Paul Walmsley 2018-12-20 21:31 ` Rob Herring 2018-12-20 21:31 ` Rob Herring 2019-04-06 23:14 ` Paul Walmsley 2019-04-06 23:14 ` Paul Walmsley 2019-04-06 23:14 ` Paul Walmsley 2018-12-16 23:35 ` [PATCH 0/7] arch: riscv: add DT file support, starting with the SiFive HiFive-U Paul Walmsley 2018-12-16 23:35 ` Paul Walmsley
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20181215052154.24347-6-paul.walmsley@sifive.com \ --to=paul.walmsley@sifive.com \ --cc=aou@eecs.berkeley.edu \ --cc=devicetree@vger.kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-riscv@lists.infradead.org \ --cc=mark.rutland@arm.com \ --cc=palmer@sifive.com \ --cc=paul@pwsan.com \ --cc=robh+dt@kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.