From: Marc Zyngier <marc.zyngier@arm.com> To: "Paolo Bonzini" <pbonzini@redhat.com>, "Radim Krčmář" <rkrcmar@redhat.com> Cc: Punit Agrawal <punit.agrawal@arm.com>, kvm@vger.kernel.org, "Gustavo A . R . Silva" <gustavo@embeddedor.com>, Will Deacon <will.deacon@arm.com>, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, Lukas Braun <koomi@moshbit.net> Subject: [PATCH 15/28] KVM: arm64: Clarify explanation of STAGE2_PGTABLE_LEVELS Date: Wed, 19 Dec 2018 18:03:36 +0000 [thread overview] Message-ID: <20181219180349.242681-16-marc.zyngier@arm.com> (raw) In-Reply-To: <20181219180349.242681-1-marc.zyngier@arm.com> From: Christoffer Dall <christoffer.dall@arm.com> In attempting to re-construct the logic for our stage 2 page table layout I found the reasoning in the comment explaining how we calculate the number of levels used for stage 2 page tables a bit backwards. This commit attempts to clarify the comment, to make it slightly easier to read without having the Arm ARM open on the right page. While we're at it, fixup a typo in a comment that was recently changed. Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> --- arch/arm64/include/asm/stage2_pgtable.h | 16 +++++++--------- virt/kvm/arm/mmu.c | 2 +- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/arch/arm64/include/asm/stage2_pgtable.h b/arch/arm64/include/asm/stage2_pgtable.h index d352f6df8d2c..5412fa40825e 100644 --- a/arch/arm64/include/asm/stage2_pgtable.h +++ b/arch/arm64/include/asm/stage2_pgtable.h @@ -30,16 +30,14 @@ #define pt_levels_pgdir_shift(lvls) ARM64_HW_PGTABLE_LEVEL_SHIFT(4 - (lvls)) /* - * The hardware supports concatenation of up to 16 tables at stage2 entry level - * and we use the feature whenever possible. + * The hardware supports concatenation of up to 16 tables at stage2 entry + * level and we use the feature whenever possible, which means we resolve 4 + * additional bits of address at the entry level. * - * Now, the minimum number of bits resolved at any level is (PAGE_SHIFT - 3). - * On arm64, the smallest PAGE_SIZE supported is 4k, which means - * (PAGE_SHIFT - 3) > 4 holds for all page sizes. - * This implies, the total number of page table levels at stage2 expected - * by the hardware is actually the number of levels required for (IPA_SHIFT - 4) - * in normal translations(e.g, stage1), since we cannot have another level in - * the range (IPA_SHIFT, IPA_SHIFT - 4). + * This implies, the total number of page table levels required for + * IPA_SHIFT at stage2 expected by the hardware can be calculated using + * the same logic used for the (non-collapsable) stage1 page tables but for + * (IPA_SHIFT - 4). */ #define stage2_pgtable_levels(ipa) ARM64_HW_PGTABLE_LEVELS((ipa) - 4) #define kvm_stage2_levels(kvm) VTCR_EL2_LVLS(kvm->arch.vtcr) diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c index 2dcff38868d4..f605514395a1 100644 --- a/virt/kvm/arm/mmu.c +++ b/virt/kvm/arm/mmu.c @@ -1356,7 +1356,7 @@ static bool transparent_hugepage_adjust(kvm_pfn_t *pfnp, phys_addr_t *ipap) struct page *page = pfn_to_page(pfn); /* - * PageTransCompoungMap() returns true for THP and + * PageTransCompoundMap() returns true for THP and * hugetlbfs. Make sure the adjustment is done only for THP * pages. */ -- 2.19.2
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <marc.zyngier@arm.com> To: "Paolo Bonzini" <pbonzini@redhat.com>, "Radim Krčmář" <rkrcmar@redhat.com> Cc: "Mark Rutland" <mark.rutland@arm.com>, "Punit Agrawal" <punit.agrawal@arm.com>, kvm@vger.kernel.org, "Julien Thierry" <julien.thierry@arm.com>, "Gustavo A . R . Silva" <gustavo@embeddedor.com>, "Will Deacon" <will.deacon@arm.com>, "Christoffer Dall" <christoffer.dall@arm.com>, linux-arm-kernel@lists.infradead.org, punitagrawal@gmail.com, "Alex Bennée" <alex.bennee@linaro.org>, kvmarm@lists.cs.columbia.edu, "Suzuki Poulose" <suzuki.poulose@arm.com>, "Lukas Braun" <koomi@moshbit.net> Subject: [PATCH 15/28] KVM: arm64: Clarify explanation of STAGE2_PGTABLE_LEVELS Date: Wed, 19 Dec 2018 18:03:36 +0000 [thread overview] Message-ID: <20181219180349.242681-16-marc.zyngier@arm.com> (raw) In-Reply-To: <20181219180349.242681-1-marc.zyngier@arm.com> From: Christoffer Dall <christoffer.dall@arm.com> In attempting to re-construct the logic for our stage 2 page table layout I found the reasoning in the comment explaining how we calculate the number of levels used for stage 2 page tables a bit backwards. This commit attempts to clarify the comment, to make it slightly easier to read without having the Arm ARM open on the right page. While we're at it, fixup a typo in a comment that was recently changed. Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> --- arch/arm64/include/asm/stage2_pgtable.h | 16 +++++++--------- virt/kvm/arm/mmu.c | 2 +- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/arch/arm64/include/asm/stage2_pgtable.h b/arch/arm64/include/asm/stage2_pgtable.h index d352f6df8d2c..5412fa40825e 100644 --- a/arch/arm64/include/asm/stage2_pgtable.h +++ b/arch/arm64/include/asm/stage2_pgtable.h @@ -30,16 +30,14 @@ #define pt_levels_pgdir_shift(lvls) ARM64_HW_PGTABLE_LEVEL_SHIFT(4 - (lvls)) /* - * The hardware supports concatenation of up to 16 tables at stage2 entry level - * and we use the feature whenever possible. + * The hardware supports concatenation of up to 16 tables at stage2 entry + * level and we use the feature whenever possible, which means we resolve 4 + * additional bits of address at the entry level. * - * Now, the minimum number of bits resolved at any level is (PAGE_SHIFT - 3). - * On arm64, the smallest PAGE_SIZE supported is 4k, which means - * (PAGE_SHIFT - 3) > 4 holds for all page sizes. - * This implies, the total number of page table levels at stage2 expected - * by the hardware is actually the number of levels required for (IPA_SHIFT - 4) - * in normal translations(e.g, stage1), since we cannot have another level in - * the range (IPA_SHIFT, IPA_SHIFT - 4). + * This implies, the total number of page table levels required for + * IPA_SHIFT at stage2 expected by the hardware can be calculated using + * the same logic used for the (non-collapsable) stage1 page tables but for + * (IPA_SHIFT - 4). */ #define stage2_pgtable_levels(ipa) ARM64_HW_PGTABLE_LEVELS((ipa) - 4) #define kvm_stage2_levels(kvm) VTCR_EL2_LVLS(kvm->arch.vtcr) diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c index 2dcff38868d4..f605514395a1 100644 --- a/virt/kvm/arm/mmu.c +++ b/virt/kvm/arm/mmu.c @@ -1356,7 +1356,7 @@ static bool transparent_hugepage_adjust(kvm_pfn_t *pfnp, phys_addr_t *ipap) struct page *page = pfn_to_page(pfn); /* - * PageTransCompoungMap() returns true for THP and + * PageTransCompoundMap() returns true for THP and * hugetlbfs. Make sure the adjustment is done only for THP * pages. */ -- 2.19.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2018-12-19 18:03 UTC|newest] Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-12-19 18:03 [GIT PULL] KVM/arm updates for 4.21 Marc Zyngier 2018-12-19 18:03 ` Marc Zyngier 2018-12-19 18:03 ` [PATCH 01/28] arm64: KVM: Skip MMIO insn after emulation Marc Zyngier 2018-12-19 18:03 ` Marc Zyngier 2018-12-19 18:03 ` [PATCH 02/28] arm64: KVM: Consistently advance singlestep when emulating instructions Marc Zyngier 2018-12-19 18:03 ` Marc Zyngier 2018-12-19 18:03 ` [PATCH 03/28] KVM: arm/arm64: Fix VMID alloc race by reverting to lock-less Marc Zyngier 2018-12-19 18:03 ` Marc Zyngier 2018-12-19 18:03 ` [PATCH 04/28] KVM: arm/arm64: Log PSTATE for unhandled sysregs Marc Zyngier 2018-12-19 18:03 ` Marc Zyngier 2018-12-19 18:03 ` [PATCH 05/28] KVM: arm/arm64: vgic-v2: Set active_source to 0 when restoring state Marc Zyngier 2018-12-19 18:03 ` Marc Zyngier 2018-12-19 18:03 ` [PATCH 06/28] KVM: arm/arm64: Share common code in user_mem_abort() Marc Zyngier 2018-12-19 18:03 ` Marc Zyngier 2018-12-19 18:03 ` [PATCH 07/28] KVM: arm/arm64: Re-factor setting the Stage 2 entry to exec on fault Marc Zyngier 2018-12-19 18:03 ` Marc Zyngier 2018-12-19 18:03 ` [PATCH 08/28] KVM: arm/arm64: Introduce helpers to manipulate page table entries Marc Zyngier 2018-12-19 18:03 ` Marc Zyngier 2018-12-19 18:03 ` [PATCH 09/28] KVM: arm64: Support dirty page tracking for PUD hugepages Marc Zyngier 2018-12-19 18:03 ` Marc Zyngier 2018-12-19 18:03 ` [PATCH 10/28] KVM: arm64: Support PUD hugepage in stage2_is_exec() Marc Zyngier 2018-12-19 18:03 ` Marc Zyngier 2018-12-19 18:03 ` [PATCH 11/28] KVM: arm64: Support handling access faults for PUD hugepages Marc Zyngier 2018-12-19 18:03 ` Marc Zyngier 2018-12-19 18:03 ` [PATCH 12/28] KVM: arm64: Update age handlers to support " Marc Zyngier 2018-12-19 18:03 ` Marc Zyngier 2018-12-19 18:03 ` [PATCH 13/28] KVM: arm64: Add support for creating PUD hugepages at stage 2 Marc Zyngier 2018-12-19 18:03 ` Marc Zyngier 2018-12-19 18:03 ` [PATCH 14/28] KVM: arm/arm64: vgic: Do not cond_resched_lock() with IRQs disabled Marc Zyngier 2018-12-19 18:03 ` Marc Zyngier 2018-12-19 18:03 ` Marc Zyngier [this message] 2018-12-19 18:03 ` [PATCH 15/28] KVM: arm64: Clarify explanation of STAGE2_PGTABLE_LEVELS Marc Zyngier 2018-12-19 18:03 ` [PATCH 16/28] KVM: arm/arm64: vgic: Cap SPIs to the VM-defined maximum Marc Zyngier 2018-12-19 18:03 ` Marc Zyngier 2018-12-19 18:03 ` [PATCH 17/28] KVM: arm/arm64: vgic: Fix off-by-one bug in vgic_get_irq() Marc Zyngier 2018-12-19 18:03 ` Marc Zyngier 2018-12-19 18:03 ` [PATCH 18/28] KVM: arm/arm64: vgic: Consider priority and active state for pending irq Marc Zyngier 2018-12-19 18:03 ` Marc Zyngier 2018-12-19 18:03 ` [PATCH 19/28] KVM: arm/arm64: Fixup the kvm_exit tracepoint Marc Zyngier 2018-12-19 18:03 ` Marc Zyngier 2018-12-19 18:03 ` [PATCH 20/28] KVM: arm/arm64: Remove arch timer workqueue Marc Zyngier 2018-12-19 18:03 ` Marc Zyngier 2018-12-19 18:03 ` [PATCH 21/28] KVM: arm/arm64: arch_timer: Simplify kvm_timer_vcpu_terminate Marc Zyngier 2018-12-19 18:03 ` Marc Zyngier 2018-12-19 18:03 ` [PATCH 22/28] KVM: arm64: Make vcpu const in vcpu_read_sys_reg Marc Zyngier 2018-12-19 18:03 ` Marc Zyngier 2018-12-19 18:03 ` [PATCH 23/28] arm64: KVM: Add trapped system register access tracepoint Marc Zyngier 2018-12-19 18:03 ` Marc Zyngier 2018-12-19 18:03 ` [PATCH 24/28] arm/arm64: KVM: vgic: Force VM halt when changing the active state of GICv3 PPIs/SGIs Marc Zyngier 2018-12-19 18:03 ` Marc Zyngier 2018-12-19 18:03 ` [PATCH 25/28] KVM: arm/arm64: Fix unintended stage 2 PMD mappings Marc Zyngier 2018-12-19 18:03 ` Marc Zyngier 2018-12-19 18:03 ` [PATCH 26/28] arm64: KVM: Avoid setting the upper 32 bits of VTCR_EL2 to 1 Marc Zyngier 2018-12-19 18:03 ` Marc Zyngier 2018-12-19 18:03 ` [PATCH 27/28] arm/arm64: KVM: Add ARM_EXCEPTION_IS_TRAP macro Marc Zyngier 2018-12-19 18:03 ` Marc Zyngier 2018-12-19 18:03 ` [PATCH 28/28] arm: KVM: Add S2_PMD_{MASK,SIZE} constants Marc Zyngier 2018-12-19 18:03 ` Marc Zyngier 2018-12-19 19:34 ` [GIT PULL] KVM/arm updates for 4.21 Paolo Bonzini 2018-12-19 19:34 ` Paolo Bonzini
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