From: Eric Auger <eric.auger@redhat.com> To: eric.auger.pro@gmail.com, eric.auger@redhat.com, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, joro@8bytes.org, alex.williamson@redhat.com, jacob.jun.pan@linux.intel.com, yi.l.liu@linux.intel.com, jean-philippe.brucker@arm.com, will.deacon@arm.com, robin.murphy@arm.com Cc: kevin.tian@intel.com, ashok.raj@intel.com, marc.zyngier@arm.com, christoffer.dall@arm.com, peter.maydell@linaro.org Subject: [RFC v3 09/21] iommu/smmuv3: Get prepared for nested stage support Date: Tue, 8 Jan 2019 11:26:21 +0100 [thread overview] Message-ID: <20190108102633.17482-10-eric.auger@redhat.com> (raw) In-Reply-To: <20190108102633.17482-1-eric.auger@redhat.com> To allow nested stage support, we need to store both stage 1 and stage 2 configurations (and remove the former union). arm_smmu_write_strtab_ent() is modified to write both stage fields in the STE. We add a nested_bypass field to the S1 configuration as the first stage can be bypassed. Also the guest may force the STE to abort: this information gets stored into the nested_abort field. Only S2 stage is "finalized" as the host does not configure S1 CD, guest does. Signed-off-by: Eric Auger <eric.auger@redhat.com> --- v1 -> v2: - invalidate the STE before moving from a live STE config to another - add the nested_abort and nested_bypass fields --- drivers/iommu/arm-smmu-v3.c | 43 ++++++++++++++++++++++++++++--------- 1 file changed, 33 insertions(+), 10 deletions(-) diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index 9af68266bbb1..9716a301d9ae 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -212,6 +212,7 @@ #define STRTAB_STE_0_CFG_BYPASS 4 #define STRTAB_STE_0_CFG_S1_TRANS 5 #define STRTAB_STE_0_CFG_S2_TRANS 6 +#define STRTAB_STE_0_CFG_NESTED 7 #define STRTAB_STE_0_S1FMT GENMASK_ULL(5, 4) #define STRTAB_STE_0_S1FMT_LINEAR 0 @@ -491,6 +492,10 @@ struct arm_smmu_strtab_l1_desc { struct arm_smmu_s1_cfg { __le64 *cdptr; dma_addr_t cdptr_dma; + /* in nested mode, tells s1 must be bypassed */ + bool nested_bypass; + /* in nested mode, abort is forced by guest */ + bool nested_abort; struct arm_smmu_ctx_desc { u16 asid; @@ -515,6 +520,7 @@ struct arm_smmu_strtab_ent { * configured according to the domain type. */ bool assigned; + bool nested; struct arm_smmu_s1_cfg *s1_cfg; struct arm_smmu_s2_cfg *s2_cfg; }; @@ -629,10 +635,8 @@ struct arm_smmu_domain { bool non_strict; enum arm_smmu_domain_stage stage; - union { - struct arm_smmu_s1_cfg s1_cfg; - struct arm_smmu_s2_cfg s2_cfg; - }; + struct arm_smmu_s1_cfg s1_cfg; + struct arm_smmu_s2_cfg s2_cfg; struct iommu_domain domain; @@ -1139,10 +1143,11 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid, break; case STRTAB_STE_0_CFG_S1_TRANS: case STRTAB_STE_0_CFG_S2_TRANS: + case STRTAB_STE_0_CFG_NESTED: ste_live = true; break; case STRTAB_STE_0_CFG_ABORT: - if (disable_bypass) + if (disable_bypass || ste->nested) break; default: BUG(); /* STE corruption */ @@ -1154,7 +1159,8 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid, /* Bypass/fault */ if (!ste->assigned || !(ste->s1_cfg || ste->s2_cfg)) { - if (!ste->assigned && disable_bypass) + if ((!ste->assigned && disable_bypass) || + (ste->s1_cfg && ste->s1_cfg->nested_abort)) val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_ABORT); else val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_BYPASS); @@ -1172,8 +1178,17 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid, return; } + if (ste->nested && ste_live) { + /* + * When enabling nested, the STE may be transitionning from + * s2 to nested and back. Invalidate the STE before changing it. + */ + dst[0] = cpu_to_le64(0); + arm_smmu_sync_ste_for_sid(smmu, sid); + val = STRTAB_STE_0_V; + } + if (ste->s1_cfg) { - BUG_ON(ste_live); dst[1] = cpu_to_le64( FIELD_PREP(STRTAB_STE_1_S1CIR, STRTAB_STE_1_S1C_CACHE_WBRA) | FIELD_PREP(STRTAB_STE_1_S1COR, STRTAB_STE_1_S1C_CACHE_WBRA) | @@ -1187,12 +1202,12 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid, !(smmu->features & ARM_SMMU_FEAT_STALL_FORCE)) dst[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD); - val |= (ste->s1_cfg->cdptr_dma & STRTAB_STE_0_S1CTXPTR_MASK) | - FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS); + if (!ste->s1_cfg->nested_bypass) + val |= (ste->s1_cfg->cdptr_dma & STRTAB_STE_0_S1CTXPTR_MASK) | + FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS); } if (ste->s2_cfg) { - BUG_ON(ste_live); dst[2] = cpu_to_le64( FIELD_PREP(STRTAB_STE_2_S2VMID, ste->s2_cfg->vmid) | FIELD_PREP(STRTAB_STE_2_VTCR, ste->s2_cfg->vtcr) | @@ -1454,6 +1469,10 @@ static void arm_smmu_tlb_inv_context(void *cookie) cmd.opcode = CMDQ_OP_TLBI_NH_ASID; cmd.tlbi.asid = smmu_domain->s1_cfg.cd.asid; cmd.tlbi.vmid = 0; + } else if (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED) { + cmd.opcode = CMDQ_OP_TLBI_NH_ASID; + cmd.tlbi.asid = smmu_domain->s1_cfg.cd.asid; + cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; } else { cmd.opcode = CMDQ_OP_TLBI_S12_VMALL; cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; @@ -1484,6 +1503,10 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size, if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { cmd.opcode = CMDQ_OP_TLBI_NH_VA; cmd.tlbi.asid = smmu_domain->s1_cfg.cd.asid; + } else if (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED) { + cmd.opcode = CMDQ_OP_TLBI_NH_VA; + cmd.tlbi.asid = smmu_domain->s1_cfg.cd.asid; + cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; } else { cmd.opcode = CMDQ_OP_TLBI_S2_IPA; cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; -- 2.17.2
WARNING: multiple messages have this Message-ID (diff)
From: Eric Auger <eric.auger-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> To: eric.auger.pro-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, eric.auger-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, kvm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, kvmarm-FPEHb7Xf0XXUo1n7N8X6UoWGPAHP3yOg@public.gmane.org, joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org, alex.williamson-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, jacob.jun.pan-VuQAYsv1563Yd54FQh9/CA@public.gmane.org, yi.l.liu-VuQAYsv1563Yd54FQh9/CA@public.gmane.org, jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org, will.deacon-5wv7dgnIgG8@public.gmane.org, robin.murphy-5wv7dgnIgG8@public.gmane.org Cc: marc.zyngier-5wv7dgnIgG8@public.gmane.org, peter.maydell-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, kevin.tian-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, ashok.raj-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, christoffer.dall-5wv7dgnIgG8@public.gmane.org Subject: [RFC v3 09/21] iommu/smmuv3: Get prepared for nested stage support Date: Tue, 8 Jan 2019 11:26:21 +0100 [thread overview] Message-ID: <20190108102633.17482-10-eric.auger@redhat.com> (raw) In-Reply-To: <20190108102633.17482-1-eric.auger-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> To allow nested stage support, we need to store both stage 1 and stage 2 configurations (and remove the former union). arm_smmu_write_strtab_ent() is modified to write both stage fields in the STE. We add a nested_bypass field to the S1 configuration as the first stage can be bypassed. Also the guest may force the STE to abort: this information gets stored into the nested_abort field. Only S2 stage is "finalized" as the host does not configure S1 CD, guest does. Signed-off-by: Eric Auger <eric.auger-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> --- v1 -> v2: - invalidate the STE before moving from a live STE config to another - add the nested_abort and nested_bypass fields --- drivers/iommu/arm-smmu-v3.c | 43 ++++++++++++++++++++++++++++--------- 1 file changed, 33 insertions(+), 10 deletions(-) diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index 9af68266bbb1..9716a301d9ae 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -212,6 +212,7 @@ #define STRTAB_STE_0_CFG_BYPASS 4 #define STRTAB_STE_0_CFG_S1_TRANS 5 #define STRTAB_STE_0_CFG_S2_TRANS 6 +#define STRTAB_STE_0_CFG_NESTED 7 #define STRTAB_STE_0_S1FMT GENMASK_ULL(5, 4) #define STRTAB_STE_0_S1FMT_LINEAR 0 @@ -491,6 +492,10 @@ struct arm_smmu_strtab_l1_desc { struct arm_smmu_s1_cfg { __le64 *cdptr; dma_addr_t cdptr_dma; + /* in nested mode, tells s1 must be bypassed */ + bool nested_bypass; + /* in nested mode, abort is forced by guest */ + bool nested_abort; struct arm_smmu_ctx_desc { u16 asid; @@ -515,6 +520,7 @@ struct arm_smmu_strtab_ent { * configured according to the domain type. */ bool assigned; + bool nested; struct arm_smmu_s1_cfg *s1_cfg; struct arm_smmu_s2_cfg *s2_cfg; }; @@ -629,10 +635,8 @@ struct arm_smmu_domain { bool non_strict; enum arm_smmu_domain_stage stage; - union { - struct arm_smmu_s1_cfg s1_cfg; - struct arm_smmu_s2_cfg s2_cfg; - }; + struct arm_smmu_s1_cfg s1_cfg; + struct arm_smmu_s2_cfg s2_cfg; struct iommu_domain domain; @@ -1139,10 +1143,11 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid, break; case STRTAB_STE_0_CFG_S1_TRANS: case STRTAB_STE_0_CFG_S2_TRANS: + case STRTAB_STE_0_CFG_NESTED: ste_live = true; break; case STRTAB_STE_0_CFG_ABORT: - if (disable_bypass) + if (disable_bypass || ste->nested) break; default: BUG(); /* STE corruption */ @@ -1154,7 +1159,8 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid, /* Bypass/fault */ if (!ste->assigned || !(ste->s1_cfg || ste->s2_cfg)) { - if (!ste->assigned && disable_bypass) + if ((!ste->assigned && disable_bypass) || + (ste->s1_cfg && ste->s1_cfg->nested_abort)) val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_ABORT); else val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_BYPASS); @@ -1172,8 +1178,17 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid, return; } + if (ste->nested && ste_live) { + /* + * When enabling nested, the STE may be transitionning from + * s2 to nested and back. Invalidate the STE before changing it. + */ + dst[0] = cpu_to_le64(0); + arm_smmu_sync_ste_for_sid(smmu, sid); + val = STRTAB_STE_0_V; + } + if (ste->s1_cfg) { - BUG_ON(ste_live); dst[1] = cpu_to_le64( FIELD_PREP(STRTAB_STE_1_S1CIR, STRTAB_STE_1_S1C_CACHE_WBRA) | FIELD_PREP(STRTAB_STE_1_S1COR, STRTAB_STE_1_S1C_CACHE_WBRA) | @@ -1187,12 +1202,12 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid, !(smmu->features & ARM_SMMU_FEAT_STALL_FORCE)) dst[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD); - val |= (ste->s1_cfg->cdptr_dma & STRTAB_STE_0_S1CTXPTR_MASK) | - FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS); + if (!ste->s1_cfg->nested_bypass) + val |= (ste->s1_cfg->cdptr_dma & STRTAB_STE_0_S1CTXPTR_MASK) | + FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS); } if (ste->s2_cfg) { - BUG_ON(ste_live); dst[2] = cpu_to_le64( FIELD_PREP(STRTAB_STE_2_S2VMID, ste->s2_cfg->vmid) | FIELD_PREP(STRTAB_STE_2_VTCR, ste->s2_cfg->vtcr) | @@ -1454,6 +1469,10 @@ static void arm_smmu_tlb_inv_context(void *cookie) cmd.opcode = CMDQ_OP_TLBI_NH_ASID; cmd.tlbi.asid = smmu_domain->s1_cfg.cd.asid; cmd.tlbi.vmid = 0; + } else if (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED) { + cmd.opcode = CMDQ_OP_TLBI_NH_ASID; + cmd.tlbi.asid = smmu_domain->s1_cfg.cd.asid; + cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; } else { cmd.opcode = CMDQ_OP_TLBI_S12_VMALL; cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; @@ -1484,6 +1503,10 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size, if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { cmd.opcode = CMDQ_OP_TLBI_NH_VA; cmd.tlbi.asid = smmu_domain->s1_cfg.cd.asid; + } else if (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED) { + cmd.opcode = CMDQ_OP_TLBI_NH_VA; + cmd.tlbi.asid = smmu_domain->s1_cfg.cd.asid; + cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; } else { cmd.opcode = CMDQ_OP_TLBI_S2_IPA; cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; -- 2.17.2
next prev parent reply other threads:[~2019-01-08 10:27 UTC|newest] Thread overview: 86+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-01-08 10:26 [RFC v3 00/21] SMMUv3 Nested Stage Setup Eric Auger 2019-01-08 10:26 ` Eric Auger 2019-01-08 10:26 ` [RFC v3 01/21] iommu: Introduce set_pasid_table API Eric Auger 2019-01-11 18:16 ` Jean-Philippe Brucker 2019-01-11 18:16 ` Jean-Philippe Brucker 2019-01-25 8:39 ` Auger Eric 2019-01-25 8:55 ` Auger Eric 2019-01-25 10:33 ` Jean-Philippe Brucker 2019-01-11 18:43 ` Alex Williamson 2019-01-11 18:43 ` Alex Williamson 2019-01-25 9:20 ` Auger Eric 2019-01-08 10:26 ` [RFC v3 02/21] iommu: Introduce cache_invalidate API Eric Auger 2019-01-11 21:30 ` Alex Williamson 2019-01-11 21:30 ` Alex Williamson 2019-01-25 16:49 ` Auger Eric 2019-01-28 17:32 ` Jean-Philippe Brucker 2019-01-28 17:32 ` Jean-Philippe Brucker 2019-01-29 17:49 ` Auger Eric 2019-01-29 23:16 ` Alex Williamson 2019-01-30 8:48 ` Auger Eric 2019-01-08 10:26 ` [RFC v3 03/21] iommu: Introduce bind_guest_msi Eric Auger 2019-01-08 10:26 ` Eric Auger 2019-01-11 22:44 ` Alex Williamson 2019-01-11 22:44 ` Alex Williamson 2019-01-25 17:51 ` Auger Eric 2019-01-25 18:11 ` Auger Eric 2019-01-08 10:26 ` [RFC v3 04/21] vfio: VFIO_IOMMU_SET_PASID_TABLE Eric Auger 2019-01-08 10:26 ` Eric Auger 2019-01-11 22:50 ` Alex Williamson 2019-01-15 21:34 ` Auger Eric 2019-01-08 10:26 ` [RFC v3 05/21] vfio: VFIO_IOMMU_CACHE_INVALIDATE Eric Auger 2019-01-08 10:26 ` [RFC v3 06/21] vfio: VFIO_IOMMU_BIND_MSI Eric Auger 2019-01-08 10:26 ` Eric Auger 2019-01-11 23:02 ` Alex Williamson 2019-01-11 23:23 ` Alex Williamson 2019-01-08 10:26 ` [RFC v3 07/21] iommu/arm-smmu-v3: Link domains and devices Eric Auger 2019-01-08 10:26 ` Eric Auger 2019-01-08 10:26 ` [RFC v3 08/21] iommu/arm-smmu-v3: Maintain a SID->device structure Eric Auger 2019-01-08 10:26 ` Eric Auger [this message] 2019-01-08 10:26 ` [RFC v3 09/21] iommu/smmuv3: Get prepared for nested stage support Eric Auger 2019-01-11 16:04 ` Jean-Philippe Brucker 2019-01-25 19:27 ` Robin Murphy 2019-01-08 10:26 ` [RFC v3 10/21] iommu/smmuv3: Implement set_pasid_table Eric Auger 2019-01-08 10:26 ` [RFC v3 11/21] iommu/smmuv3: Implement cache_invalidate Eric Auger 2019-01-08 10:26 ` Eric Auger 2019-01-11 16:59 ` Jean-Philippe Brucker 2019-01-08 10:26 ` [RFC v3 12/21] dma-iommu: Implement NESTED_MSI cookie Eric Auger 2019-01-08 10:26 ` Eric Auger 2019-01-08 10:26 ` [RFC v3 13/21] iommu/smmuv3: Implement bind_guest_msi Eric Auger 2019-01-08 10:26 ` [RFC v3 14/21] iommu: introduce device fault data Eric Auger 2019-01-08 10:26 ` Eric Auger [not found] ` <20190108102633.17482-15-eric.auger-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> 2019-01-10 18:45 ` Jacob Pan 2019-01-11 11:06 ` Jean-Philippe Brucker 2019-01-14 22:32 ` Jacob Pan 2019-01-14 22:32 ` Jacob Pan 2019-01-16 15:52 ` Jean-Philippe Brucker 2019-01-16 18:33 ` Auger Eric 2019-01-15 21:27 ` Auger Eric 2019-01-16 16:54 ` Jean-Philippe Brucker 2019-01-16 16:54 ` Jean-Philippe Brucker 2019-01-08 10:26 ` [RFC v3 15/21] driver core: add per device iommu param Eric Auger 2019-01-08 10:26 ` Eric Auger 2019-01-08 10:26 ` [RFC v3 16/21] iommu: introduce device fault report API Eric Auger 2019-01-08 10:26 ` Eric Auger 2019-01-08 10:26 ` [RFC v3 17/21] iommu/smmuv3: Report non recoverable faults Eric Auger 2019-01-08 10:26 ` Eric Auger 2019-01-11 17:46 ` Jean-Philippe Brucker 2019-01-15 21:06 ` Auger Eric 2019-01-15 21:06 ` Auger Eric 2019-01-16 12:25 ` Jean-Philippe Brucker 2019-01-16 12:25 ` Jean-Philippe Brucker 2019-01-16 12:49 ` Auger Eric 2019-01-16 12:49 ` Auger Eric 2019-01-08 10:26 ` [RFC v3 18/21] vfio-pci: Add a new VFIO_REGION_TYPE_NESTED region type Eric Auger 2019-01-08 10:26 ` Eric Auger 2019-01-11 23:58 ` Alex Williamson 2019-01-14 20:48 ` Auger Eric 2019-01-14 23:04 ` Alex Williamson 2019-01-15 21:56 ` Auger Eric 2019-01-08 10:26 ` [RFC v3 19/21] vfio-pci: Register an iommu fault handler Eric Auger 2019-01-08 10:26 ` Eric Auger 2019-01-08 10:26 ` [RFC v3 20/21] vfio-pci: Add VFIO_PCI_DMA_FAULT_IRQ_INDEX Eric Auger 2019-01-08 10:26 ` Eric Auger 2019-01-08 10:26 ` [RFC v3 21/21] vfio: Document nested stage control Eric Auger 2019-01-08 10:26 ` Eric Auger 2019-01-18 10:02 ` [RFC v3 00/21] SMMUv3 Nested Stage Setup Auger Eric
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