From: Jonas Bonn <jonas@norrbonn.se> To: linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org Cc: Jonas Bonn <jonas@norrbonn.se>, Nicolas Ferre <nicolas.ferre@microchip.com>, Mark Brown <broonie@kernel.org>, Alexandre Belloni <alexandre.belloni@bootlin.com>, Ludovic Desroches <ludovic.desroches@microchip.com>, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 2/2] spi-atmel: support inter-word delay Date: Fri, 25 Jan 2019 13:24:25 +0100 [thread overview] Message-ID: <20190125122425.30676-3-jonas@norrbonn.se> (raw) In-Reply-To: <20190125122425.30676-1-jonas@norrbonn.se> If the SPI slave requires an inter-word delay, configure the DLYBCT register accordingly. Tested on a SAMA5D2 board (derived from SAMA5D2-Xplained reference board). Signed-off-by: Jonas Bonn <jonas@norrbonn.se> CC: Nicolas Ferre <nicolas.ferre@microchip.com> CC: Mark Brown <broonie@kernel.org> CC: Alexandre Belloni <alexandre.belloni@bootlin.com> CC: Ludovic Desroches <ludovic.desroches@microchip.com> CC: linux-spi@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org --- drivers/spi/spi-atmel.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c index 74fddcd3282b..24445bfbd74e 100644 --- a/drivers/spi/spi-atmel.c +++ b/drivers/spi/spi-atmel.c @@ -1209,13 +1209,21 @@ static int atmel_spi_setup(struct spi_device *spi) csr |= SPI_BIT(CSAAT); /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs. - * - * DLYBCT would add delays between words, slowing down transfers. - * It could potentially be useful to cope with DMA bottlenecks, but - * in those cases it's probably best to just use a lower bitrate. */ csr |= SPI_BF(DLYBS, 0); - csr |= SPI_BF(DLYBCT, 0); + + /* DLYBCT adds delays between words. This is useful for slow devices + * that need a bit of time to setup the next transfer. + */ + if (spi->word_delay) { + csr |= SPI_BF(DLYBCT, + clamp_t(u8, + (as->spi_clk/1000000*spi->word_delay)>>5, + 1, 255)); + } else { + csr |= SPI_BF(DLYBCT, 0); + } + /* chipselect must have been muxed as GPIO (e.g. in board setup) */ npcs_pin = (unsigned long)spi->controller_data; -- 2.19.1
WARNING: multiple messages have this Message-ID (diff)
From: Jonas Bonn <jonas@norrbonn.se> To: linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>, Jonas Bonn <jonas@norrbonn.se>, Ludovic Desroches <ludovic.desroches@microchip.com>, Mark Brown <broonie@kernel.org>, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 2/2] spi-atmel: support inter-word delay Date: Fri, 25 Jan 2019 13:24:25 +0100 [thread overview] Message-ID: <20190125122425.30676-3-jonas@norrbonn.se> (raw) In-Reply-To: <20190125122425.30676-1-jonas@norrbonn.se> If the SPI slave requires an inter-word delay, configure the DLYBCT register accordingly. Tested on a SAMA5D2 board (derived from SAMA5D2-Xplained reference board). Signed-off-by: Jonas Bonn <jonas@norrbonn.se> CC: Nicolas Ferre <nicolas.ferre@microchip.com> CC: Mark Brown <broonie@kernel.org> CC: Alexandre Belloni <alexandre.belloni@bootlin.com> CC: Ludovic Desroches <ludovic.desroches@microchip.com> CC: linux-spi@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org --- drivers/spi/spi-atmel.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c index 74fddcd3282b..24445bfbd74e 100644 --- a/drivers/spi/spi-atmel.c +++ b/drivers/spi/spi-atmel.c @@ -1209,13 +1209,21 @@ static int atmel_spi_setup(struct spi_device *spi) csr |= SPI_BIT(CSAAT); /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs. - * - * DLYBCT would add delays between words, slowing down transfers. - * It could potentially be useful to cope with DMA bottlenecks, but - * in those cases it's probably best to just use a lower bitrate. */ csr |= SPI_BF(DLYBS, 0); - csr |= SPI_BF(DLYBCT, 0); + + /* DLYBCT adds delays between words. This is useful for slow devices + * that need a bit of time to setup the next transfer. + */ + if (spi->word_delay) { + csr |= SPI_BF(DLYBCT, + clamp_t(u8, + (as->spi_clk/1000000*spi->word_delay)>>5, + 1, 255)); + } else { + csr |= SPI_BF(DLYBCT, 0); + } + /* chipselect must have been muxed as GPIO (e.g. in board setup) */ npcs_pin = (unsigned long)spi->controller_data; -- 2.19.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-01-25 12:24 UTC|newest] Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-01-25 12:24 [PATCH v2 0/2] spi: support inter-word delays Jonas Bonn 2019-01-25 12:24 ` [PATCH v2 1/2] spi: support inter-word delay requirement for devices Jonas Bonn 2019-01-25 12:24 ` Jonas Bonn [this message] 2019-01-25 12:24 ` [PATCH v2 2/2] spi-atmel: support inter-word delay Jonas Bonn
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