From: Chen-Yu Tsai <wens@csie.org> To: Ulf Hansson <ulf.hansson@linaro.org>, Maxime Ripard <maxime.ripard@bootlin.com> Cc: Chen-Yu Tsai <wens@csie.org>, linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Chris Blake <chrisrblake93@gmail.com>, stable@vger.kernel.org Subject: [PATCH v2 1/3] mmc: sunxi: Disable HS-DDR mode for H5 eMMC controller by default Date: Tue, 5 Feb 2019 23:42:23 +0800 [thread overview] Message-ID: <20190205154225.14264-2-wens@csie.org> (raw) In-Reply-To: <20190205154225.14264-1-wens@csie.org> Some H5 boards seem to not have proper trace lengths for eMMC to be able to use the default setting for the delay chains under HS-DDR mode. These include the Bananapi M2+ H5 and NanoPi NEO Core2. However the Libre Computer ALL-H3-CC-H5 works just fine. For the H5 (at least for now), default to not enabling HS-DDR modes in the driver, and expect the device tree to signal HS-DDR capability on boards that work. Reported-by: Chris Blake <chrisrblake93@gmail.com> Fixes: 07bafc1e3536 ("mmc: sunxi: Use new timing mode for A64 eMMC controller") Cc: <stable@vger.kernel.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- drivers/mmc/host/sunxi-mmc.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c index 279e326e397e..7415af8c8ff6 100644 --- a/drivers/mmc/host/sunxi-mmc.c +++ b/drivers/mmc/host/sunxi-mmc.c @@ -1399,7 +1399,16 @@ static int sunxi_mmc_probe(struct platform_device *pdev) mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ; - if (host->cfg->clk_delays || host->use_new_timings) + /* + * Some H5 devices do not have signal traces precise enough to + * use HS DDR mode for their eMMC chips. + * + * We still enable HS DDR modes for all the other controller + * variants that support them. + */ + if ((host->cfg->clk_delays || host->use_new_timings) && + !of_device_is_compatible(pdev->dev.of_node, + "allwinner,sun50i-h5-emmc")) mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR; ret = mmc_of_parse(mmc); -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Chen-Yu Tsai <wens@csie.org> To: Ulf Hansson <ulf.hansson@linaro.org>, Maxime Ripard <maxime.ripard@bootlin.com> Cc: devicetree@vger.kernel.org, Chris Blake <chrisrblake93@gmail.com>, linux-mmc@vger.kernel.org, linux-sunxi@googlegroups.com, stable@vger.kernel.org, linux-kernel@vger.kernel.org, Chen-Yu Tsai <wens@csie.org>, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 1/3] mmc: sunxi: Disable HS-DDR mode for H5 eMMC controller by default Date: Tue, 5 Feb 2019 23:42:23 +0800 [thread overview] Message-ID: <20190205154225.14264-2-wens@csie.org> (raw) In-Reply-To: <20190205154225.14264-1-wens@csie.org> Some H5 boards seem to not have proper trace lengths for eMMC to be able to use the default setting for the delay chains under HS-DDR mode. These include the Bananapi M2+ H5 and NanoPi NEO Core2. However the Libre Computer ALL-H3-CC-H5 works just fine. For the H5 (at least for now), default to not enabling HS-DDR modes in the driver, and expect the device tree to signal HS-DDR capability on boards that work. Reported-by: Chris Blake <chrisrblake93@gmail.com> Fixes: 07bafc1e3536 ("mmc: sunxi: Use new timing mode for A64 eMMC controller") Cc: <stable@vger.kernel.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- drivers/mmc/host/sunxi-mmc.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c index 279e326e397e..7415af8c8ff6 100644 --- a/drivers/mmc/host/sunxi-mmc.c +++ b/drivers/mmc/host/sunxi-mmc.c @@ -1399,7 +1399,16 @@ static int sunxi_mmc_probe(struct platform_device *pdev) mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ; - if (host->cfg->clk_delays || host->use_new_timings) + /* + * Some H5 devices do not have signal traces precise enough to + * use HS DDR mode for their eMMC chips. + * + * We still enable HS DDR modes for all the other controller + * variants that support them. + */ + if ((host->cfg->clk_delays || host->use_new_timings) && + !of_device_is_compatible(pdev->dev.of_node, + "allwinner,sun50i-h5-emmc")) mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR; ret = mmc_of_parse(mmc); -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-02-05 15:42 UTC|newest] Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-02-05 15:42 [PATCH v2 0/3] mmc: sunxi: Fix eMMC usage on H5 boards Chen-Yu Tsai 2019-02-05 15:42 ` Chen-Yu Tsai 2019-02-05 15:42 ` Chen-Yu Tsai 2019-02-05 15:42 ` Chen-Yu Tsai [this message] 2019-02-05 15:42 ` [PATCH v2 1/3] mmc: sunxi: Disable HS-DDR mode for H5 eMMC controller by default Chen-Yu Tsai 2019-02-06 15:14 ` Ulf Hansson 2019-02-06 15:14 ` Ulf Hansson 2019-02-06 15:14 ` Ulf Hansson 2019-02-05 15:42 ` [PATCH v2 2/3] mmc: sunxi: Filter out unsupported modes declared in the device tree Chen-Yu Tsai 2019-02-05 15:42 ` Chen-Yu Tsai 2019-02-05 15:42 ` Chen-Yu Tsai 2019-02-06 12:20 ` Maxime Ripard 2019-02-06 12:20 ` Maxime Ripard 2019-02-06 15:14 ` Ulf Hansson 2019-02-06 15:14 ` Ulf Hansson 2019-02-06 15:14 ` Ulf Hansson 2019-02-05 15:42 ` [PATCH v2 3/3] arm64: dts: allwinner: h5: libretech-all-h3-cc: Mark eMMC HS-DDR 3.3V capable Chen-Yu Tsai 2019-02-05 15:42 ` Chen-Yu Tsai 2019-02-05 15:42 ` Chen-Yu Tsai 2019-02-06 12:20 ` Maxime Ripard 2019-02-06 12:20 ` Maxime Ripard 2019-02-06 12:20 ` Maxime Ripard
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