From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH v2 00/13] Enable/disable gamma/csc dynamically and fix C8
Date: Tue, 5 Feb 2019 18:08:35 +0200 [thread overview]
Message-ID: <20190205160848.24662-1-ville.syrjala@linux.intel.com> (raw)
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Rebase of the gamma/csc series. The last patch is new to fix Matt's
observation that we need something to configure the DSPCNTR gamma/csc
bits correctly during modeset.
Ville Syrjälä (13):
drm/i915: Split the gamma/csc enable bits from the plane_ctl()
function
drm/i915: Precompute gamma_mode
drm/i915: Constify the state arguments to the color management stuff
drm/i915: Pull GAMMA_MODE write out from haswell_load_luts()
drm/i915: Split color mgmt based on single vs. double buffered
registers
drm/i915: Move LUT programming to happen after vblank waits
drm/i915: Populate gamma_mode for all platforms
drm/i915: Track pipe gamma enable/disable in crtc state
drm/i915: Track pipe csc enable in crtc state
drm/i915: Turn off pipe gamma when it's not needed
drm/i915: Turn off pipe CSC when it's not needed
drm/i915: Disable pipe gamma when C8 pixel format is used
drm/i915: Update DSPCNTR gamma/csc bits during crtc_enable()
drivers/gpu/drm/i915/i915_drv.h | 16 +-
drivers/gpu/drm/i915/i915_reg.h | 14 +-
drivers/gpu/drm/i915/intel_atomic_plane.c | 5 +
drivers/gpu/drm/i915/intel_color.c | 381 ++++++++++++++--------
drivers/gpu/drm/i915/intel_display.c | 283 ++++++++++++----
drivers/gpu/drm/i915/intel_drv.h | 14 +-
drivers/gpu/drm/i915/intel_sprite.c | 67 +++-
7 files changed, 568 insertions(+), 212 deletions(-)
--
2.19.2
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next reply other threads:[~2019-02-05 16:08 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-05 16:08 Ville Syrjala [this message]
2019-02-05 16:08 ` [PATCH v2 01/13] drm/i915: Split the gamma/csc enable bits from the plane_ctl() function Ville Syrjala
2019-02-05 16:08 ` [PATCH v2 02/13] drm/i915: Precompute gamma_mode Ville Syrjala
2019-02-05 16:08 ` [PATCH v2 03/13] drm/i915: Constify the state arguments to the color management stuff Ville Syrjala
2019-02-05 16:08 ` [PATCH v2 04/13] drm/i915: Pull GAMMA_MODE write out from haswell_load_luts() Ville Syrjala
2019-02-05 16:08 ` [PATCH v2 05/13] drm/i915: Split color mgmt based on single vs. double buffered registers Ville Syrjala
2019-02-05 16:08 ` [PATCH v2 06/13] drm/i915: Move LUT programming to happen after vblank waits Ville Syrjala
2019-02-07 15:46 ` Maarten Lankhorst
2019-02-07 19:24 ` Ville Syrjälä
2019-02-05 16:08 ` [PATCH v2 07/13] drm/i915: Populate gamma_mode for all platforms Ville Syrjala
2019-02-07 15:49 ` Maarten Lankhorst
2019-02-07 16:27 ` Ville Syrjälä
2019-02-07 17:27 ` Ville Syrjälä
2019-02-08 8:51 ` Maarten Lankhorst
2019-02-05 16:08 ` [PATCH v2 08/13] drm/i915: Track pipe gamma enable/disable in crtc state Ville Syrjala
2019-02-05 16:08 ` [PATCH v2 09/13] drm/i915: Track pipe csc enable " Ville Syrjala
2019-02-05 16:08 ` [PATCH v2 10/13] drm/i915: Turn off pipe gamma when it's not needed Ville Syrjala
2019-02-05 16:08 ` [PATCH v2 11/13] drm/i915: Turn off pipe CSC " Ville Syrjala
2019-02-05 16:08 ` [PATCH v2 12/13] drm/i915: Disable pipe gamma when C8 pixel format is used Ville Syrjala
2019-02-05 16:08 ` [PATCH v2 13/13] drm/i915: Update DSPCNTR gamma/csc bits during crtc_enable() Ville Syrjala
2019-02-07 15:58 ` Maarten Lankhorst
2019-02-07 16:29 ` Ville Syrjälä
2019-02-05 16:57 ` ✗ Fi.CI.CHECKPATCH: warning for Enable/disable gamma/csc dynamically and fix C8 (rev2) Patchwork
2019-02-05 17:02 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-02-05 17:24 ` ✓ Fi.CI.BAT: success " Patchwork
2019-02-05 21:19 ` ✓ Fi.CI.IGT: " Patchwork
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