From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 1/2] drm/i915: Bump skl+ wm blocks to 11 bits
Date: Tue, 5 Feb 2019 22:50:55 +0200 [thread overview]
Message-ID: <20190205205056.30081-1-ville.syrjala@linux.intel.com> (raw)
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
On icl the plane watermark blocks field is 11 bits. Bump our define to
match so that readout won't ignore the extra bit. We can safely do this
for older platforms too since the unused bits are hardwired to zero.
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 12964b0fbc54..2be34e13af78 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6000,7 +6000,7 @@ enum {
#define PLANE_WM_EN (1 << 31)
#define PLANE_WM_LINES_SHIFT 14
#define PLANE_WM_LINES_MASK 0x1f
-#define PLANE_WM_BLOCKS_MASK 0x3ff
+#define PLANE_WM_BLOCKS_MASK 0x7ff /* skl+: 10 bits, icl+ 11 bits */
#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
--
2.19.2
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next reply other threads:[~2019-02-05 20:50 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-05 20:50 Ville Syrjala [this message]
2019-02-05 20:50 ` [PATCH 2/2] drm/i915: Just use icl+ definition for PLANE_WM blocks field Ville Syrjala
2019-02-06 1:04 ` Souza, Jose
2019-02-06 13:18 ` Ville Syrjälä
2019-02-07 0:21 ` Souza, Jose
2019-02-05 21:34 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Bump skl+ wm blocks to 11 bits Patchwork
2019-02-06 0:47 ` [PATCH 1/2] " Souza, Jose
2019-02-06 3:28 ` ✓ Fi.CI.IGT: success for series starting with [1/2] " Patchwork
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