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From: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
To: Maxime Ripard
	<maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org>,
	Linus Walleij
	<linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Cc: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org
Subject: [PATCH 8/9] ARM: dts: sun9i: a80-optimus: Enable GMAC
Date: Wed,  6 Feb 2019 11:32:38 +0800	[thread overview]
Message-ID: <20190206033239.3619-9-wens@csie.org> (raw)
In-Reply-To: <20190206033239.3619-1-wens-jdAy2FN1RRM@public.gmane.org>

The A80 Optimus has a Realtek RTL8211E ethernet PHY which uses RGMII to
talk to the MAC. The PHY is powered by 2 regulators: cldo1 for the PHY's
core logic and gpio1-ldo for I/O. The latter also powers the SoC side
pins. As there is no binding to model a second regulator supply for the
PHY, it is omitted. It is however properly modeled for the PIO.

Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
---
 arch/arm/boot/dts/sun9i-a80-optimus.dts | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index 9c25176e69dc..864715ec3cb0 100644
--- a/arch/arm/boot/dts/sun9i-a80-optimus.dts
+++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts
@@ -120,6 +120,19 @@
 	status = "okay";
 };
 
+&gmac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac_rgmii_pins>;
+	phy = <&phy1>;
+	phy-mode = "rgmii";
+	phy-supply = <&reg_cldo1>;
+	status = "okay";
+
+	phy1: ethernet-phy@1 {
+		reg = <1>;
+	};
+};
+
 &mmc0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc0_pins>;
@@ -391,6 +404,14 @@
 				 */
 				regulator-min-microvolt = <3300000>;
 				regulator-max-microvolt = <3300000>;
+				/*
+				 * The PHY requires 20ms after all voltages
+				 * are applied until core logic is ready and
+				 * 30ms after the reset pin is de-asserted.
+				 * Set a 100ms delay to account for PMIC
+				 * ramp time and board traces.
+				 */
+				regulator-enable-ramp-delay = <100000>;
 				regulator-name = "vcc-gmac-phy";
 			};
 
-- 
2.20.1

WARNING: multiple messages have this Message-ID (diff)
From: Chen-Yu Tsai <wens@csie.org>
To: Maxime Ripard <maxime.ripard@bootlin.com>,
	Linus Walleij <linus.walleij@linaro.org>
Cc: Chen-Yu Tsai <wens@csie.org>,
	linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-sunxi@googlegroups.com
Subject: [PATCH 8/9] ARM: dts: sun9i: a80-optimus: Enable GMAC
Date: Wed,  6 Feb 2019 11:32:38 +0800	[thread overview]
Message-ID: <20190206033239.3619-9-wens@csie.org> (raw)
In-Reply-To: <20190206033239.3619-1-wens@csie.org>

The A80 Optimus has a Realtek RTL8211E ethernet PHY which uses RGMII to
talk to the MAC. The PHY is powered by 2 regulators: cldo1 for the PHY's
core logic and gpio1-ldo for I/O. The latter also powers the SoC side
pins. As there is no binding to model a second regulator supply for the
PHY, it is omitted. It is however properly modeled for the PIO.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun9i-a80-optimus.dts | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index 9c25176e69dc..864715ec3cb0 100644
--- a/arch/arm/boot/dts/sun9i-a80-optimus.dts
+++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts
@@ -120,6 +120,19 @@
 	status = "okay";
 };
 
+&gmac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac_rgmii_pins>;
+	phy = <&phy1>;
+	phy-mode = "rgmii";
+	phy-supply = <&reg_cldo1>;
+	status = "okay";
+
+	phy1: ethernet-phy@1 {
+		reg = <1>;
+	};
+};
+
 &mmc0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc0_pins>;
@@ -391,6 +404,14 @@
 				 */
 				regulator-min-microvolt = <3300000>;
 				regulator-max-microvolt = <3300000>;
+				/*
+				 * The PHY requires 20ms after all voltages
+				 * are applied until core logic is ready and
+				 * 30ms after the reset pin is de-asserted.
+				 * Set a 100ms delay to account for PMIC
+				 * ramp time and board traces.
+				 */
+				regulator-enable-ramp-delay = <100000>;
 				regulator-name = "vcc-gmac-phy";
 			};
 
-- 
2.20.1


WARNING: multiple messages have this Message-ID (diff)
From: Chen-Yu Tsai <wens@csie.org>
To: Maxime Ripard <maxime.ripard@bootlin.com>,
	Linus Walleij <linus.walleij@linaro.org>
Cc: devicetree@vger.kernel.org, linux-sunxi@googlegroups.com,
	linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org,
	Chen-Yu Tsai <wens@csie.org>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH 8/9] ARM: dts: sun9i: a80-optimus: Enable GMAC
Date: Wed,  6 Feb 2019 11:32:38 +0800	[thread overview]
Message-ID: <20190206033239.3619-9-wens@csie.org> (raw)
In-Reply-To: <20190206033239.3619-1-wens@csie.org>

The A80 Optimus has a Realtek RTL8211E ethernet PHY which uses RGMII to
talk to the MAC. The PHY is powered by 2 regulators: cldo1 for the PHY's
core logic and gpio1-ldo for I/O. The latter also powers the SoC side
pins. As there is no binding to model a second regulator supply for the
PHY, it is omitted. It is however properly modeled for the PIO.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun9i-a80-optimus.dts | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index 9c25176e69dc..864715ec3cb0 100644
--- a/arch/arm/boot/dts/sun9i-a80-optimus.dts
+++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts
@@ -120,6 +120,19 @@
 	status = "okay";
 };
 
+&gmac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac_rgmii_pins>;
+	phy = <&phy1>;
+	phy-mode = "rgmii";
+	phy-supply = <&reg_cldo1>;
+	status = "okay";
+
+	phy1: ethernet-phy@1 {
+		reg = <1>;
+	};
+};
+
 &mmc0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc0_pins>;
@@ -391,6 +404,14 @@
 				 */
 				regulator-min-microvolt = <3300000>;
 				regulator-max-microvolt = <3300000>;
+				/*
+				 * The PHY requires 20ms after all voltages
+				 * are applied until core logic is ready and
+				 * 30ms after the reset pin is de-asserted.
+				 * Set a 100ms delay to account for PMIC
+				 * ramp time and board traces.
+				 */
+				regulator-enable-ramp-delay = <100000>;
 				regulator-name = "vcc-gmac-phy";
 			};
 
-- 
2.20.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2019-02-06  3:32 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-02-06  3:32 [PATCH 0/9] ARM: sun9i: a80: Enable GMAC Chen-Yu Tsai
2019-02-06  3:32 ` Chen-Yu Tsai
2019-02-06  3:32 ` Chen-Yu Tsai
2019-02-06  3:32 ` [PATCH 4/9] ARM: dts: sun9i: cubieboard4: Add GPIO pin-bank regulator supplies Chen-Yu Tsai
2019-02-06  3:32   ` Chen-Yu Tsai
     [not found] ` <20190206033239.3619-1-wens-jdAy2FN1RRM@public.gmane.org>
2019-02-06  3:32   ` [PATCH 1/9] pinctrl: sunxi: Support I/O bias voltage setting on A80 Chen-Yu Tsai
2019-02-06  3:32     ` Chen-Yu Tsai
2019-02-06  3:32     ` Chen-Yu Tsai
     [not found]     ` <20190206033239.3619-2-wens-jdAy2FN1RRM@public.gmane.org>
2019-02-06  8:14       ` Linus Walleij
2019-02-06  8:14         ` Linus Walleij
2019-02-06  8:14         ` Linus Walleij
2019-02-06 10:22         ` [linux-sunxi] " Chen-Yu Tsai
2019-02-06 10:22           ` Chen-Yu Tsai
2019-02-06 10:22           ` Chen-Yu Tsai
2019-02-06 12:17       ` Maxime Ripard
2019-02-06 12:17         ` Maxime Ripard
2019-02-06 12:17         ` Maxime Ripard
2019-02-11  8:20       ` Linus Walleij
2019-02-11  8:20         ` Linus Walleij
2019-02-11  8:20         ` Linus Walleij
2019-02-13 11:31         ` Chen-Yu Tsai
2019-02-13 11:31           ` Chen-Yu Tsai
2019-02-13 11:31           ` Chen-Yu Tsai
2019-02-06  3:32   ` [PATCH 2/9] ARM: dts: sun9i: a80-optimus: Add node for AXP809's unused dc1sw regulator Chen-Yu Tsai
2019-02-06  3:32     ` Chen-Yu Tsai
2019-02-06  3:32     ` Chen-Yu Tsai
2019-02-06  3:32   ` [PATCH 3/9] ARM: dts: sun9i: a80-optimus: Add GPIO pin-bank regulator supplies Chen-Yu Tsai
2019-02-06  3:32     ` Chen-Yu Tsai
2019-02-06  3:32     ` Chen-Yu Tsai
2019-02-06  3:32   ` [PATCH 5/9] ARM: dts: sun9i: Add GMAC clock node Chen-Yu Tsai
2019-02-06  3:32     ` Chen-Yu Tsai
2019-02-06  3:32     ` Chen-Yu Tsai
2019-02-06  3:32   ` [PATCH 6/9] ARM: dts: sun9i: Add A80 GMAC gigabit ethernet controller node Chen-Yu Tsai
2019-02-06  3:32     ` Chen-Yu Tsai
2019-02-06  3:32     ` Chen-Yu Tsai
2019-02-06  3:32   ` [PATCH 7/9] ARM: dts: sun9i: Add A80 GMAC RGMII pinmux setting Chen-Yu Tsai
2019-02-06  3:32     ` Chen-Yu Tsai
2019-02-06  3:32     ` Chen-Yu Tsai
2019-02-06  3:32   ` Chen-Yu Tsai [this message]
2019-02-06  3:32     ` [PATCH 8/9] ARM: dts: sun9i: a80-optimus: Enable GMAC Chen-Yu Tsai
2019-02-06  3:32     ` Chen-Yu Tsai
2019-02-06  3:32   ` [PATCH 9/9] ARM: dts: sun9i: cubieboard4: " Chen-Yu Tsai
2019-02-06  3:32     ` Chen-Yu Tsai
2019-02-06  3:32     ` Chen-Yu Tsai
2019-02-06 12:16   ` [PATCH 0/9] ARM: sun9i: a80: " Maxime Ripard
2019-02-06 12:16     ` Maxime Ripard
2019-02-06 12:16     ` Maxime Ripard

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