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From: Weiyi Lu <weiyi.lu@mediatek.com>
To: Nicolas Boichat <drinkcat@chromium.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Rob Herring <robh@kernel.org>
Cc: James Liao <jamesjj.liao@mediatek.com>,
	Fan Chen <fan.chen@mediatek.com>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-mediatek@lists.infradead.org>,
	<srv_heupstream@mediatek.com>, Weiyi Lu <weiyi.lu@mediatek.com>
Subject: [PATCH v5 04/14] soc: mediatek: Refactor polling timeout and documentation
Date: Tue, 19 Mar 2019 16:01:30 +0800	[thread overview]
Message-ID: <20190319080140.24055-5-weiyi.lu@mediatek.com> (raw)
In-Reply-To: <20190319080140.24055-1-weiyi.lu@mediatek.com>

Use USEC_PER_SEC to indicate the polling timeout directly.
And add documentation of scp_domain_data.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
 drivers/soc/mediatek/mtk-scpsys.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index 9f52f501178b..2855111b221a 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -21,7 +21,7 @@
 #include <dt-bindings/power/mt8173-power.h>
 
 #define MTK_POLL_DELAY_US   10
-#define MTK_POLL_TIMEOUT    (jiffies_to_usecs(HZ))
+#define MTK_POLL_TIMEOUT    USEC_PER_SEC
 
 #define MTK_SCPD_ACTIVE_WAKEUP		BIT(0)
 #define MTK_SCPD_FWAIT_SRAM		BIT(1)
@@ -108,6 +108,18 @@ static const char * const clk_names[] = {
 
 #define MAX_CLKS	3
 
+/**
+ * struct scp_domain_data - scp domain data for power on/off flow
+ * @name: The domain name.
+ * @sta_mask: The mask for power on/off status bit.
+ * @ctl_offs: The offset for main power control register.
+ * @sram_pdn_bits: The mask for sram power control bits.
+ * @sram_pdn_ack_bits: The mask for sram power control acked bits.
+ * @bus_prot_mask: The mask for single step bus protection.
+ * @clk_id: The basic clock needs to be enabled before enabling certain
+ *          power domains.
+ * @caps: The flag for active wake-up action.
+ */
 struct scp_domain_data {
 	const char *name;
 	u32 sta_mask;
-- 
2.18.0


WARNING: multiple messages have this Message-ID (diff)
From: Weiyi Lu <weiyi.lu@mediatek.com>
To: Nicolas Boichat <drinkcat@chromium.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Rob Herring <robh@kernel.org>
Cc: James Liao <jamesjj.liao@mediatek.com>,
	Fan Chen <fan.chen@mediatek.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
	srv_heupstream@mediatek.com, Weiyi Lu <weiyi.lu@mediatek.com>
Subject: [PATCH v5 04/14] soc: mediatek: Refactor polling timeout and documentation
Date: Tue, 19 Mar 2019 16:01:30 +0800	[thread overview]
Message-ID: <20190319080140.24055-5-weiyi.lu@mediatek.com> (raw)
In-Reply-To: <20190319080140.24055-1-weiyi.lu@mediatek.com>

Use USEC_PER_SEC to indicate the polling timeout directly.
And add documentation of scp_domain_data.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
 drivers/soc/mediatek/mtk-scpsys.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index 9f52f501178b..2855111b221a 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -21,7 +21,7 @@
 #include <dt-bindings/power/mt8173-power.h>
 
 #define MTK_POLL_DELAY_US   10
-#define MTK_POLL_TIMEOUT    (jiffies_to_usecs(HZ))
+#define MTK_POLL_TIMEOUT    USEC_PER_SEC
 
 #define MTK_SCPD_ACTIVE_WAKEUP		BIT(0)
 #define MTK_SCPD_FWAIT_SRAM		BIT(1)
@@ -108,6 +108,18 @@ static const char * const clk_names[] = {
 
 #define MAX_CLKS	3
 
+/**
+ * struct scp_domain_data - scp domain data for power on/off flow
+ * @name: The domain name.
+ * @sta_mask: The mask for power on/off status bit.
+ * @ctl_offs: The offset for main power control register.
+ * @sram_pdn_bits: The mask for sram power control bits.
+ * @sram_pdn_ack_bits: The mask for sram power control acked bits.
+ * @bus_prot_mask: The mask for single step bus protection.
+ * @clk_id: The basic clock needs to be enabled before enabling certain
+ *          power domains.
+ * @caps: The flag for active wake-up action.
+ */
 struct scp_domain_data {
 	const char *name;
 	u32 sta_mask;
-- 
2.18.0

WARNING: multiple messages have this Message-ID (diff)
From: Weiyi Lu <weiyi.lu@mediatek.com>
To: Nicolas Boichat <drinkcat@chromium.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Rob Herring <robh@kernel.org>
Cc: James Liao <jamesjj.liao@mediatek.com>,
	Weiyi Lu <weiyi.lu@mediatek.com>,
	srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org,
	Fan Chen <fan.chen@mediatek.com>,
	linux-mediatek@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 04/14] soc: mediatek: Refactor polling timeout and documentation
Date: Tue, 19 Mar 2019 16:01:30 +0800	[thread overview]
Message-ID: <20190319080140.24055-5-weiyi.lu@mediatek.com> (raw)
In-Reply-To: <20190319080140.24055-1-weiyi.lu@mediatek.com>

Use USEC_PER_SEC to indicate the polling timeout directly.
And add documentation of scp_domain_data.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
 drivers/soc/mediatek/mtk-scpsys.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index 9f52f501178b..2855111b221a 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -21,7 +21,7 @@
 #include <dt-bindings/power/mt8173-power.h>
 
 #define MTK_POLL_DELAY_US   10
-#define MTK_POLL_TIMEOUT    (jiffies_to_usecs(HZ))
+#define MTK_POLL_TIMEOUT    USEC_PER_SEC
 
 #define MTK_SCPD_ACTIVE_WAKEUP		BIT(0)
 #define MTK_SCPD_FWAIT_SRAM		BIT(1)
@@ -108,6 +108,18 @@ static const char * const clk_names[] = {
 
 #define MAX_CLKS	3
 
+/**
+ * struct scp_domain_data - scp domain data for power on/off flow
+ * @name: The domain name.
+ * @sta_mask: The mask for power on/off status bit.
+ * @ctl_offs: The offset for main power control register.
+ * @sram_pdn_bits: The mask for sram power control bits.
+ * @sram_pdn_ack_bits: The mask for sram power control acked bits.
+ * @bus_prot_mask: The mask for single step bus protection.
+ * @clk_id: The basic clock needs to be enabled before enabling certain
+ *          power domains.
+ * @caps: The flag for active wake-up action.
+ */
 struct scp_domain_data {
 	const char *name;
 	u32 sta_mask;
-- 
2.18.0


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  parent reply	other threads:[~2019-03-19  8:02 UTC|newest]

Thread overview: 81+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-19  8:01 [PATCH v5 00/14] Mediatek MT8183 scpsys support Weiyi Lu
2019-03-19  8:01 ` Weiyi Lu
2019-03-19  8:01 ` Weiyi Lu
2019-03-19  8:01 ` [PATCH v5 01/14] dt-bindings: mediatek: Add property to mt8183 smi-common Weiyi Lu
2019-03-19  8:01   ` Weiyi Lu
2019-03-19  8:01   ` Weiyi Lu
2019-03-19  8:01 ` [PATCH v5 02/14] dt-bindings: soc: Add MT8183 power dt-bindings Weiyi Lu
2019-03-19  8:01   ` Weiyi Lu
2019-03-19  8:01   ` Weiyi Lu
2019-03-19  8:01 ` [PATCH v5 03/14] soc: mediatek: Switch to SPDX license identifier Weiyi Lu
2019-03-19  8:01   ` Weiyi Lu
2019-03-19  8:01   ` Weiyi Lu
2019-03-19  8:01 ` Weiyi Lu [this message]
2019-03-19  8:01   ` [PATCH v5 04/14] soc: mediatek: Refactor polling timeout and documentation Weiyi Lu
2019-03-19  8:01   ` Weiyi Lu
2019-03-19 11:45   ` Nicolas Boichat
2019-03-19 11:45     ` Nicolas Boichat
2019-03-19 11:45     ` Nicolas Boichat
2019-06-19  9:11     ` Weiyi Lu
2019-06-19  9:11       ` Weiyi Lu
2019-06-19  9:11       ` Weiyi Lu
2019-03-19  8:01 ` [PATCH v5 05/14] soc: mediatek: Refactor regulator control Weiyi Lu
2019-03-19  8:01   ` Weiyi Lu
2019-03-19  8:01   ` Weiyi Lu
2019-03-19  8:01 ` [PATCH v5 06/14] soc: mediatek: Refactor clock control Weiyi Lu
2019-03-19  8:01   ` Weiyi Lu
2019-03-19  8:01   ` Weiyi Lu
2019-03-19 12:02   ` Nicolas Boichat
2019-03-19 12:02     ` Nicolas Boichat
2019-03-19 12:02     ` Nicolas Boichat
2019-06-19  9:19     ` Weiyi Lu
2019-06-19  9:19       ` Weiyi Lu
2019-06-19  9:19       ` Weiyi Lu
2019-03-19  8:01 ` [PATCH v5 07/14] soc: mediatek: Refactor sram control Weiyi Lu
2019-03-19  8:01   ` Weiyi Lu
2019-03-19  8:01   ` Weiyi Lu
2019-03-19 12:07   ` Nicolas Boichat
2019-03-19 12:07     ` Nicolas Boichat
2019-03-19 12:07     ` Nicolas Boichat
2019-06-19  9:30     ` Weiyi Lu
2019-06-19  9:30       ` Weiyi Lu
2019-06-19  9:30       ` Weiyi Lu
2019-03-19  8:01 ` [PATCH v5 08/14] soc: mediatek: Refactor bus protection control Weiyi Lu
2019-03-19  8:01   ` Weiyi Lu
2019-03-19  8:01   ` Weiyi Lu
2019-03-19 12:09   ` Nicolas Boichat
2019-03-19 12:09     ` Nicolas Boichat
2019-03-19 12:09     ` Nicolas Boichat
2019-06-19  9:31     ` Weiyi Lu
2019-06-19  9:31       ` Weiyi Lu
2019-06-19  9:31       ` Weiyi Lu
2019-03-19  8:01 ` [PATCH v5 09/14] soc: mediatek: Add basic_clk_name to scp_power_data Weiyi Lu
2019-03-19  8:01   ` Weiyi Lu
2019-03-19  8:01   ` Weiyi Lu
2019-03-21  6:02   ` Nicolas Boichat
2019-03-21  6:02     ` Nicolas Boichat
2019-03-21  6:02     ` Nicolas Boichat
2019-06-19  9:36     ` Weiyi Lu
2019-06-19  9:36       ` Weiyi Lu
2019-06-19  9:36       ` Weiyi Lu
2019-03-19  8:01 ` [PATCH v5 10/14] soc: mediatek: Add multiple step bus protection control Weiyi Lu
2019-03-19  8:01   ` Weiyi Lu
2019-03-19  8:01   ` Weiyi Lu
2019-03-21  5:57   ` Nicolas Boichat
2019-03-21  5:57     ` Nicolas Boichat
2019-03-21  5:57     ` Nicolas Boichat
2019-06-19  9:43     ` Weiyi Lu
2019-06-19  9:43       ` Weiyi Lu
2019-06-19  9:43       ` Weiyi Lu
2019-03-19  8:01 ` [PATCH v5 11/14] soc: mediatek: Add subsys clock control for bus protection Weiyi Lu
2019-03-19  8:01   ` Weiyi Lu
2019-03-19  8:01   ` Weiyi Lu
2019-03-19  8:01 ` [PATCH v5 12/14] soc: mediatek: Add extra sram control Weiyi Lu
2019-03-19  8:01   ` Weiyi Lu
2019-03-19  8:01   ` Weiyi Lu
2019-03-19  8:01 ` [PATCH v5 13/14] soc: mediatek: Add MT8183 scpsys support Weiyi Lu
2019-03-19  8:01   ` Weiyi Lu
2019-03-19  8:01   ` Weiyi Lu
2019-03-19  8:01 ` [PATCH v5 14/14] arm64: dts: Add power controller device node of MT8183 Weiyi Lu
2019-03-19  8:01   ` Weiyi Lu
2019-03-19  8:01   ` Weiyi Lu

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