All of lore.kernel.org
 help / color / mirror / Atom feed
From: Kishon Vijay Abraham I <kishon@ti.com>
To: Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Rob Herring <robh+dt@kernel.org>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Arnd Bergmann <arnd@arndb.de>,
	Murali Karicheri <m-karicheri2@ti.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>,
	Jingoo Han <jingoohan1@gmail.com>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <linux-omap@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-arm-kernel@axis.com>
Subject: [PATCH v2 11/26] PCI: dwc: Fix ATU identification for designware version >= 4.80
Date: Mon, 25 Mar 2019 14:04:46 +0530	[thread overview]
Message-ID: <20190325083501.8088-12-kishon@ti.com> (raw)
In-Reply-To: <20190325083501.8088-1-kishon@ti.com>

Synopsys designware version >= 4.80 uses a separate register space
for programming ATU. The current code identifies if there exists a
separate register space by accessing the register address of ATUs
in designware version < 4.80. Accessing this address results in
abort in the case of K2G.

Fix it here by adding "version" member to struct dw_pcie. This should
be set by platform specific drivers and designware core will use it
to identify if the platform has a separate ATU space. For platforms
which hasn't populated the version member, the old method of
identification will still be used.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 drivers/pci/controller/dwc/pcie-designware.c | 14 ++++++++------
 drivers/pci/controller/dwc/pcie-designware.h |  1 +
 2 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index a14ca00f72aa..4e2f7946da89 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -358,13 +358,15 @@ void dw_pcie_setup(struct dw_pcie *pci)
 	struct device *dev = pci->dev;
 	struct device_node *np = dev->of_node;
 
-	/* Get iATU unroll support */
-	pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci);
-	dev_dbg(pci->dev, "iATU unroll: %s\n",
-		pci->iatu_unroll_enabled ? "enabled" : "disabled");
+	if (pci->version >= 0x480A || (!pci->version &&
+				       dw_pcie_iatu_unroll_enabled(pci))) {
+		pci->iatu_unroll_enabled = true;
+		if (!pci->atu_base)
+			pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
+	}
+	dev_dbg(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ?
+		"enabled" : "disabled");
 
-	if (pci->iatu_unroll_enabled && !pci->atu_base)
-		pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
 
 	ret = of_property_read_u32(np, "num-lanes", &lanes);
 	if (ret)
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index ca3a3190a6f5..90a5b1215344 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -234,6 +234,7 @@ struct dw_pcie {
 	struct pcie_port	pp;
 	struct dw_pcie_ep	ep;
 	const struct dw_pcie_ops *ops;
+	unsigned int		version;
 };
 
 #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
-- 
2.17.1


WARNING: multiple messages have this Message-ID (diff)
From: Kishon Vijay Abraham I <kishon@ti.com>
To: Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Rob Herring <robh+dt@kernel.org>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Arnd Bergmann <arnd@arndb.de>,
	Murali Karicheri <m-karicheri2@ti.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>,
	Jingoo Han <jingoohan1@gmail.com>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, linux-arm-kernel@axis.com
Subject: [PATCH v2 11/26] PCI: dwc: Fix ATU identification for designware version >= 4.80
Date: Mon, 25 Mar 2019 14:04:46 +0530	[thread overview]
Message-ID: <20190325083501.8088-12-kishon@ti.com> (raw)
In-Reply-To: <20190325083501.8088-1-kishon@ti.com>

Synopsys designware version >= 4.80 uses a separate register space
for programming ATU. The current code identifies if there exists a
separate register space by accessing the register address of ATUs
in designware version < 4.80. Accessing this address results in
abort in the case of K2G.

Fix it here by adding "version" member to struct dw_pcie. This should
be set by platform specific drivers and designware core will use it
to identify if the platform has a separate ATU space. For platforms
which hasn't populated the version member, the old method of
identification will still be used.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 drivers/pci/controller/dwc/pcie-designware.c | 14 ++++++++------
 drivers/pci/controller/dwc/pcie-designware.h |  1 +
 2 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index a14ca00f72aa..4e2f7946da89 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -358,13 +358,15 @@ void dw_pcie_setup(struct dw_pcie *pci)
 	struct device *dev = pci->dev;
 	struct device_node *np = dev->of_node;
 
-	/* Get iATU unroll support */
-	pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci);
-	dev_dbg(pci->dev, "iATU unroll: %s\n",
-		pci->iatu_unroll_enabled ? "enabled" : "disabled");
+	if (pci->version >= 0x480A || (!pci->version &&
+				       dw_pcie_iatu_unroll_enabled(pci))) {
+		pci->iatu_unroll_enabled = true;
+		if (!pci->atu_base)
+			pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
+	}
+	dev_dbg(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ?
+		"enabled" : "disabled");
 
-	if (pci->iatu_unroll_enabled && !pci->atu_base)
-		pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
 
 	ret = of_property_read_u32(np, "num-lanes", &lanes);
 	if (ret)
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index ca3a3190a6f5..90a5b1215344 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -234,6 +234,7 @@ struct dw_pcie {
 	struct pcie_port	pp;
 	struct dw_pcie_ep	ep;
 	const struct dw_pcie_ops *ops;
+	unsigned int		version;
 };
 
 #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
-- 
2.17.1

WARNING: multiple messages have this Message-ID (diff)
From: Kishon Vijay Abraham I <kishon@ti.com>
To: Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Rob Herring <robh+dt@kernel.org>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Arnd Bergmann <arnd@arndb.de>,
	Murali Karicheri <m-karicheri2@ti.com>
Cc: devicetree@vger.kernel.org,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Jingoo Han <jingoohan1@gmail.com>,
	linux-kernel@vger.kernel.org, linux-arm-kernel@axis.com,
	Kishon Vijay Abraham I <kishon@ti.com>,
	linux-pci@vger.kernel.org, linux-omap@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 11/26] PCI: dwc: Fix ATU identification for designware version >= 4.80
Date: Mon, 25 Mar 2019 14:04:46 +0530	[thread overview]
Message-ID: <20190325083501.8088-12-kishon@ti.com> (raw)
In-Reply-To: <20190325083501.8088-1-kishon@ti.com>

Synopsys designware version >= 4.80 uses a separate register space
for programming ATU. The current code identifies if there exists a
separate register space by accessing the register address of ATUs
in designware version < 4.80. Accessing this address results in
abort in the case of K2G.

Fix it here by adding "version" member to struct dw_pcie. This should
be set by platform specific drivers and designware core will use it
to identify if the platform has a separate ATU space. For platforms
which hasn't populated the version member, the old method of
identification will still be used.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 drivers/pci/controller/dwc/pcie-designware.c | 14 ++++++++------
 drivers/pci/controller/dwc/pcie-designware.h |  1 +
 2 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index a14ca00f72aa..4e2f7946da89 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -358,13 +358,15 @@ void dw_pcie_setup(struct dw_pcie *pci)
 	struct device *dev = pci->dev;
 	struct device_node *np = dev->of_node;
 
-	/* Get iATU unroll support */
-	pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci);
-	dev_dbg(pci->dev, "iATU unroll: %s\n",
-		pci->iatu_unroll_enabled ? "enabled" : "disabled");
+	if (pci->version >= 0x480A || (!pci->version &&
+				       dw_pcie_iatu_unroll_enabled(pci))) {
+		pci->iatu_unroll_enabled = true;
+		if (!pci->atu_base)
+			pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
+	}
+	dev_dbg(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ?
+		"enabled" : "disabled");
 
-	if (pci->iatu_unroll_enabled && !pci->atu_base)
-		pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
 
 	ret = of_property_read_u32(np, "num-lanes", &lanes);
 	if (ret)
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index ca3a3190a6f5..90a5b1215344 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -234,6 +234,7 @@ struct dw_pcie {
 	struct pcie_port	pp;
 	struct dw_pcie_ep	ep;
 	const struct dw_pcie_ops *ops;
+	unsigned int		version;
 };
 
 #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
-- 
2.17.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2019-03-25  8:37 UTC|newest]

Thread overview: 94+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-25  8:34 [PATCH v2 00/26] Add support for PCIe RC and EP mode in TI's AM654 SoC Kishon Vijay Abraham I
2019-03-25  8:34 ` Kishon Vijay Abraham I
2019-03-25  8:34 ` Kishon Vijay Abraham I
2019-03-25  8:34 ` [PATCH v2 01/26] PCI: keystone: Add start_link/stop_link dw_pcie_ops Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34 ` [PATCH v2 02/26] PCI: keystone: Cleanup error_irq configuration Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34 ` [PATCH v2 03/26] dt-bindings: PCI: keystone: Add "reg-names" binding information Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34 ` [PATCH v2 04/26] PCI: keystone: Perform host initialization in a single function Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34 ` [PATCH v2 05/26] PCI: keystone: Use platform_get_resource_byname to get memory resources Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34 ` [PATCH v2 06/26] PCI: keystone: Move initializations to appropriate places Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-04-13 14:30   ` Bjorn Helgaas
2019-04-13 14:30     ` Bjorn Helgaas
2019-04-15  5:34     ` Kishon Vijay Abraham I
2019-04-15  5:34       ` Kishon Vijay Abraham I
2019-04-15 12:25       ` Lorenzo Pieralisi
2019-04-15 12:25         ` Lorenzo Pieralisi
2019-03-25  8:34 ` [PATCH v2 07/26] dt-bindings: PCI: Add dt-binding to configure PCIe mode Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34 ` [PATCH v2 08/26] PCI: keystone: Explicitly set the " Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34 ` [PATCH v2 09/26] dt-bindings: PCI: Document "atu" reg-names Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34 ` [PATCH v2 10/26] PCI: dwc: Enable iATU unroll for endpoint too Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34 ` Kishon Vijay Abraham I [this message]
2019-03-25  8:34   ` [PATCH v2 11/26] PCI: dwc: Fix ATU identification for designware version >= 4.80 Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34 ` [PATCH v2 12/26] PCI: keystone: Prevent ARM32 specific code to be compiled for ARM64 Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34 ` [PATCH v2 13/26] dt-bindings: PCI: Add PCI RC dt binding documentation for AM654 Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34 ` [PATCH v2 14/26] PCI: keystone: Add support for PCIe RC in AM654x Platforms Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34 ` [PATCH v2 15/26] PCI: keystone: Invoke phy_reset API before enabling PHY Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34 ` [PATCH v2 16/26] PCI: OF: Allow of_pci_get_max_link_speed() to be used by PCI Endpoint drivers Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34 ` [PATCH v2 17/26] PCI: keystone: Add support to set the max link speed from DT Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34 ` [PATCH v2 18/26] PCI: endpoint: Add support to allocate aligned buffers to be mapped in BARs Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34 ` [PATCH v2 19/26] PCI: dwc: Add const qualifier to struct dw_pcie_ep_ops Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34 ` [PATCH v2 20/26] PCI: dwc: Fix dw_pcie_ep_find_capability to return correct capability offset Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34 ` [PATCH v2 21/26] PCI: dwc: Add callbacks for accessing dbi2 address space Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34 ` [PATCH v2 22/26] PCI: keystone: Add support for PCIe EP in AM654x Platforms Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34 ` [PATCH v2 23/26] PCI: designware-ep: Configure RESBAR to advertise the smallest size Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-04-13 16:00   ` Bjorn Helgaas
2019-04-13 16:00     ` Bjorn Helgaas
2019-04-16 13:36     ` Lorenzo Pieralisi
2019-04-16 13:36       ` Lorenzo Pieralisi
2019-03-25  8:34 ` [PATCH v2 24/26] PCI: designware-ep: Use aligned ATU window for raising MSI interrupts Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:34   ` Kishon Vijay Abraham I
2019-03-25  8:35 ` [PATCH v2 25/26] misc: pci_endpoint_test: Add support to test PCI EP in AM654x Kishon Vijay Abraham I
2019-03-25  8:35   ` Kishon Vijay Abraham I
2019-03-25  8:35   ` Kishon Vijay Abraham I
2019-03-25  8:35 ` [PATCH v2 26/26] misc: pci_endpoint_test: Fix test_reg_bar to be updated in pci_endpoint_test Kishon Vijay Abraham I
2019-03-25  8:35   ` Kishon Vijay Abraham I
2019-03-25  8:35   ` Kishon Vijay Abraham I
2019-03-25  9:36 ` [PATCH v2 00/26] Add support for PCIe RC and EP mode in TI's AM654 SoC Kishon Vijay Abraham I
2019-03-25  9:36   ` Kishon Vijay Abraham I
2019-03-25  9:36   ` Kishon Vijay Abraham I

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20190325083501.8088-12-kishon@ti.com \
    --to=kishon@ti.com \
    --cc=arnd@arndb.de \
    --cc=bhelgaas@google.com \
    --cc=devicetree@vger.kernel.org \
    --cc=gregkh@linuxfoundation.org \
    --cc=gustavo.pimentel@synopsys.com \
    --cc=jingoohan1@gmail.com \
    --cc=linux-arm-kernel@axis.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-omap@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=lorenzo.pieralisi@arm.com \
    --cc=m-karicheri2@ti.com \
    --cc=robh+dt@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.