From: Atish Patra <atish.patra@wdc.com> To: linux-kernel@vger.kernel.org Cc: Atish Patra <atish.patra@wdc.com>, Albert Ou <aou@eecs.berkeley.edu>, Anup Patel <anup@brainfault.org>, Borislav Petkov <bp@alien8.de>, Gary Guo <gary@garyguo.net>, "H. Peter Anvin" <hpa@zytor.com>, Ingo Molnar <mingo@redhat.com>, linux-riscv@lists.infradead.org, Luc Van Oostenryck <luc.vanoostenryck@gmail.com>, Palmer Dabbelt <palmer@sifive.com>, Thomas Gleixner <tglx@linutronix.de>, x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)) Subject: [2/3] RISC-V: Update tlb flush counters Date: Wed, 10 Apr 2019 15:44:48 -0700 [thread overview] Message-ID: <20190410224449.10877-3-atish.patra@wdc.com> (raw) In-Reply-To: <20190410224449.10877-1-atish.patra@wdc.com> The TLB flush counters under vmstat seems to be very helpful while debugging TLB flush performance in RISC-V. Update the counters in every TLB flush methods respectively. Signed-off-by: Atish Patra <atish.patra@wdc.com> --- arch/riscv/include/asm/tlbflush.h | 5 +++++ arch/riscv/mm/tlbflush.c | 12 ++++++++++++ 2 files changed, 17 insertions(+) diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h index 29a780ca232a..19779a083f52 100644 --- a/arch/riscv/include/asm/tlbflush.h +++ b/arch/riscv/include/asm/tlbflush.h @@ -9,6 +9,7 @@ #define _ASM_RISCV_TLBFLUSH_H #include <linux/mm_types.h> +#include <linux/vmstat.h> /* * Flush entire local TLB. 'sfence.vma' implicitly fences with the instruction @@ -16,11 +17,13 @@ */ static inline void local_flush_tlb_all(void) { + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL); __asm__ __volatile__ ("sfence.vma" : : : "memory"); } static inline void local_flush_tlb_mm(struct mm_struct *mm) { + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL); /* Flush ASID 0 so that global mappings are not affected */ __asm__ __volatile__ ("sfence.vma x0, %0" : : "r" (0) : "memory"); } @@ -28,6 +31,7 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm) static inline void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) { + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE); __asm__ __volatile__ ("sfence.vma %0, %1" : : "r" (addr), "r" (0) : "memory"); @@ -35,6 +39,7 @@ static inline void local_flush_tlb_page(struct vm_area_struct *vma, static inline void local_flush_tlb_kernel_page(unsigned long addr) { + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE); __asm__ __volatile__ ("sfence.vma %0" : : "r" (addr) : "memory"); } diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index ceee76f14a0a..8072d7da32bb 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -4,6 +4,8 @@ */ #include <linux/mm.h> +#include <linux/vmstat.h> +#include <linux/cpumask.h> #include <asm/sbi.h> #define SFENCE_VMA_FLUSH_ALL ((unsigned long) -1) @@ -110,6 +112,7 @@ static void ipi_remote_sfence_vma(void *info) unsigned long size = data->size; unsigned long i; + count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED); if (size == SFENCE_VMA_FLUSH_ALL) { local_flush_tlb_all(); } @@ -129,6 +132,8 @@ static void ipi_remote_sfence_vma_asid(void *info) unsigned long size = data->size; unsigned long i; + count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED); + /* Flush entire MM context */ if (size == SFENCE_VMA_FLUSH_ALL) { __asm__ __volatile__ ("sfence.vma x0, %0" : : "r" (asid) @@ -158,6 +163,13 @@ static void remote_sfence_vma(unsigned long start, unsigned long size) static void remote_sfence_vma_asid(cpumask_t *mask, unsigned long start, unsigned long size, unsigned long asid) { + int cpuid = smp_processor_id(); + + if (cpumask_equal(mask, cpumask_of(cpuid))) + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL); + else + count_vm_tlb_event(NR_TLB_REMOTE_FLUSH); + if (tlbi_ipi) { struct tlbi info = { .start = start, -- 2.21.0
WARNING: multiple messages have this Message-ID (diff)
From: Atish Patra <atish.patra@wdc.com> To: linux-kernel@vger.kernel.org Cc: Albert Ou <aou@eecs.berkeley.edu>, Anup Patel <anup@brainfault.org>, Palmer Dabbelt <palmer@sifive.com>, "maintainer:X86 ARCHITECTURE 32-BIT AND 64-BIT" <x86@kernel.org>, Atish Patra <atish.patra@wdc.com>, Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>, Gary Guo <gary@garyguo.net>, "H. Peter Anvin" <hpa@zytor.com>, linux-riscv@lists.infradead.org, Thomas Gleixner <tglx@linutronix.de>, Luc Van Oostenryck <luc.vanoostenryck@gmail.com> Subject: [2/3] RISC-V: Update tlb flush counters Date: Wed, 10 Apr 2019 15:44:48 -0700 [thread overview] Message-ID: <20190410224449.10877-3-atish.patra@wdc.com> (raw) In-Reply-To: <20190410224449.10877-1-atish.patra@wdc.com> The TLB flush counters under vmstat seems to be very helpful while debugging TLB flush performance in RISC-V. Update the counters in every TLB flush methods respectively. Signed-off-by: Atish Patra <atish.patra@wdc.com> --- arch/riscv/include/asm/tlbflush.h | 5 +++++ arch/riscv/mm/tlbflush.c | 12 ++++++++++++ 2 files changed, 17 insertions(+) diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h index 29a780ca232a..19779a083f52 100644 --- a/arch/riscv/include/asm/tlbflush.h +++ b/arch/riscv/include/asm/tlbflush.h @@ -9,6 +9,7 @@ #define _ASM_RISCV_TLBFLUSH_H #include <linux/mm_types.h> +#include <linux/vmstat.h> /* * Flush entire local TLB. 'sfence.vma' implicitly fences with the instruction @@ -16,11 +17,13 @@ */ static inline void local_flush_tlb_all(void) { + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL); __asm__ __volatile__ ("sfence.vma" : : : "memory"); } static inline void local_flush_tlb_mm(struct mm_struct *mm) { + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL); /* Flush ASID 0 so that global mappings are not affected */ __asm__ __volatile__ ("sfence.vma x0, %0" : : "r" (0) : "memory"); } @@ -28,6 +31,7 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm) static inline void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) { + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE); __asm__ __volatile__ ("sfence.vma %0, %1" : : "r" (addr), "r" (0) : "memory"); @@ -35,6 +39,7 @@ static inline void local_flush_tlb_page(struct vm_area_struct *vma, static inline void local_flush_tlb_kernel_page(unsigned long addr) { + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE); __asm__ __volatile__ ("sfence.vma %0" : : "r" (addr) : "memory"); } diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index ceee76f14a0a..8072d7da32bb 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -4,6 +4,8 @@ */ #include <linux/mm.h> +#include <linux/vmstat.h> +#include <linux/cpumask.h> #include <asm/sbi.h> #define SFENCE_VMA_FLUSH_ALL ((unsigned long) -1) @@ -110,6 +112,7 @@ static void ipi_remote_sfence_vma(void *info) unsigned long size = data->size; unsigned long i; + count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED); if (size == SFENCE_VMA_FLUSH_ALL) { local_flush_tlb_all(); } @@ -129,6 +132,8 @@ static void ipi_remote_sfence_vma_asid(void *info) unsigned long size = data->size; unsigned long i; + count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED); + /* Flush entire MM context */ if (size == SFENCE_VMA_FLUSH_ALL) { __asm__ __volatile__ ("sfence.vma x0, %0" : : "r" (asid) @@ -158,6 +163,13 @@ static void remote_sfence_vma(unsigned long start, unsigned long size) static void remote_sfence_vma_asid(cpumask_t *mask, unsigned long start, unsigned long size, unsigned long asid) { + int cpuid = smp_processor_id(); + + if (cpumask_equal(mask, cpumask_of(cpuid))) + count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL); + else + count_vm_tlb_event(NR_TLB_REMOTE_FLUSH); + if (tlbi_ipi) { struct tlbi info = { .start = start, -- 2.21.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2019-04-10 22:45 UTC|newest] Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-04-10 22:44 [0/3] TLB flush counters Atish Patra 2019-04-10 22:44 ` Atish Patra 2019-04-10 22:44 ` [1/3] x86: Update DEBUG_TLBFLUSH options description Atish Patra 2019-04-10 22:44 ` Atish Patra 2019-04-11 6:56 ` Christoph Hellwig 2019-04-11 6:56 ` Christoph Hellwig 2019-04-12 20:14 ` Atish Patra 2019-04-12 20:14 ` Atish Patra 2019-04-14 14:27 ` Borislav Petkov 2019-04-14 14:27 ` Borislav Petkov 2019-04-29 19:52 ` Atish Patra 2019-04-29 19:52 ` Atish Patra 2019-04-25 20:17 ` Palmer Dabbelt 2019-04-25 20:17 ` Palmer Dabbelt 2019-04-10 22:44 ` Atish Patra [this message] 2019-04-10 22:44 ` [2/3] RISC-V: Update tlb flush counters Atish Patra 2019-04-25 20:17 ` Palmer Dabbelt 2019-04-25 20:17 ` Palmer Dabbelt 2019-04-26 18:54 ` Atish Patra 2019-04-26 18:54 ` Atish Patra 2019-04-10 22:44 ` [3/3] RISC-V: Add DEBUG_TLBFLUSH option Atish Patra 2019-04-10 22:44 ` Atish Patra
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