From: Vidya Sagar <vidyas@nvidia.com>
To: lorenzo.pieralisi@arm.com, bhelgaas@google.com,
robh+dt@kernel.org, mark.rutland@arm.com,
thierry.reding@gmail.com, jonathanh@nvidia.com, kishon@ti.com,
catalin.marinas@arm.com, will.deacon@arm.com,
jingoohan1@gmail.com, gustavo.pimentel@synopsys.com
Cc: mperttunen@nvidia.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, kthota@nvidia.com,
mmaddireddy@nvidia.com, vidyas@nvidia.com, sagar.tv@gmail.com
Subject: [PATCH V4 01/16] PCI: Add #defines for some of PCIe spec r4.0 features
Date: Tue, 23 Apr 2019 13:57:15 +0530 [thread overview]
Message-ID: <20190423082730.370-2-vidyas@nvidia.com> (raw)
In-Reply-To: <20190423082730.370-1-vidyas@nvidia.com>
Add #defines only for the Data Link Feature and Physical Layer 16.0 GT/s
features.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
---
Changes from [v3]:
* None
Changes from [v2]:
* Updated commit message and description to explicitly mention that defines are
added only for some of the features and not all.
Changes from [v1]:
* None
include/uapi/linux/pci_regs.h | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index f7d3e7831fa8..4da04b1faab3 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -703,7 +703,9 @@
#define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */
#define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */
#define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */
-#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM
+#define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */
+#define PCI_EXT_CAP_ID_PL 0x26 /* Physical Layer 16.0 GT/s */
+#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL
#define PCI_EXT_CAP_DSN_SIZEOF 12
#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
@@ -1043,4 +1045,22 @@
#define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */
#define PCI_L1SS_CTL2 0x0c /* Control 2 Register */
+/* Data Link Feature */
+#define PCI_DLF_CAP 0x04 /* Capabilities Register */
+#define PCI_DLF_LOCAL_DLF_SUP_MASK 0x007fffff /* Local Data Link Feature Supported */
+#define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */
+#define PCI_DLF_STS 0x08 /* Status Register */
+#define PCI_DLF_REMOTE_DLF_SUP_MASK 0x007fffff /* Remote Data Link Feature Supported */
+#define PCI_DLF_REMOTE_DLF_SUP_VALID 0x80000000 /* Remote Data Link Feature Support Valid */
+
+/* Physical Layer 16.0 GT/s */
+#define PCI_PL_16GT_CAP 0x04 /* Capabilities Register */
+#define PCI_PL_16GT_CTRL 0x08 /* Control Register */
+#define PCI_PL_16GT_STS 0x0c /* Status Register */
+#define PCI_PL_16GT_LDPM_STS 0x10 /* Local Data Parity Mismatch Status Register */
+#define PCI_PL_16GT_FRDPM_STS 0x14 /* First Retimer Data Parity Mismatch Status Register */
+#define PCI_PL_16GT_SRDPM_STS 0x18 /* Second Retimer Data Parity Mismatch Status Register */
+#define PCI_PL_16GT_RSVD 0x1C /* Reserved */
+#define PCI_PL_16GT_LE_CTRL 0x20 /* Lane Equalization Control Register */
+
#endif /* LINUX_PCI_REGS_H */
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Vidya Sagar <vidyas@nvidia.com>
To: <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
<robh+dt@kernel.org>, <mark.rutland@arm.com>,
<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
<kishon@ti.com>, <catalin.marinas@arm.com>, <will.deacon@arm.com>,
<jingoohan1@gmail.com>, <gustavo.pimentel@synopsys.com>
Cc: <mperttunen@nvidia.com>, <linux-pci@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <kthota@nvidia.com>,
<mmaddireddy@nvidia.com>, <vidyas@nvidia.com>,
<sagar.tv@gmail.com>
Subject: [PATCH V4 01/16] PCI: Add #defines for some of PCIe spec r4.0 features
Date: Tue, 23 Apr 2019 13:57:15 +0530 [thread overview]
Message-ID: <20190423082730.370-2-vidyas@nvidia.com> (raw)
In-Reply-To: <20190423082730.370-1-vidyas@nvidia.com>
Add #defines only for the Data Link Feature and Physical Layer 16.0 GT/s
features.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
---
Changes from [v3]:
* None
Changes from [v2]:
* Updated commit message and description to explicitly mention that defines are
added only for some of the features and not all.
Changes from [v1]:
* None
include/uapi/linux/pci_regs.h | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index f7d3e7831fa8..4da04b1faab3 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -703,7 +703,9 @@
#define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */
#define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */
#define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */
-#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM
+#define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */
+#define PCI_EXT_CAP_ID_PL 0x26 /* Physical Layer 16.0 GT/s */
+#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL
#define PCI_EXT_CAP_DSN_SIZEOF 12
#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
@@ -1043,4 +1045,22 @@
#define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */
#define PCI_L1SS_CTL2 0x0c /* Control 2 Register */
+/* Data Link Feature */
+#define PCI_DLF_CAP 0x04 /* Capabilities Register */
+#define PCI_DLF_LOCAL_DLF_SUP_MASK 0x007fffff /* Local Data Link Feature Supported */
+#define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */
+#define PCI_DLF_STS 0x08 /* Status Register */
+#define PCI_DLF_REMOTE_DLF_SUP_MASK 0x007fffff /* Remote Data Link Feature Supported */
+#define PCI_DLF_REMOTE_DLF_SUP_VALID 0x80000000 /* Remote Data Link Feature Support Valid */
+
+/* Physical Layer 16.0 GT/s */
+#define PCI_PL_16GT_CAP 0x04 /* Capabilities Register */
+#define PCI_PL_16GT_CTRL 0x08 /* Control Register */
+#define PCI_PL_16GT_STS 0x0c /* Status Register */
+#define PCI_PL_16GT_LDPM_STS 0x10 /* Local Data Parity Mismatch Status Register */
+#define PCI_PL_16GT_FRDPM_STS 0x14 /* First Retimer Data Parity Mismatch Status Register */
+#define PCI_PL_16GT_SRDPM_STS 0x18 /* Second Retimer Data Parity Mismatch Status Register */
+#define PCI_PL_16GT_RSVD 0x1C /* Reserved */
+#define PCI_PL_16GT_LE_CTRL 0x20 /* Lane Equalization Control Register */
+
#endif /* LINUX_PCI_REGS_H */
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Vidya Sagar <vidyas@nvidia.com>
To: <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
<robh+dt@kernel.org>, <mark.rutland@arm.com>,
<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
<kishon@ti.com>, <catalin.marinas@arm.com>, <will.deacon@arm.com>,
<jingoohan1@gmail.com>, <gustavo.pimentel@synopsys.com>
Cc: devicetree@vger.kernel.org, mmaddireddy@nvidia.com,
kthota@nvidia.com, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, mperttunen@nvidia.com,
linux-tegra@vger.kernel.org, vidyas@nvidia.com,
linux-arm-kernel@lists.infradead.org, sagar.tv@gmail.com
Subject: [PATCH V4 01/16] PCI: Add #defines for some of PCIe spec r4.0 features
Date: Tue, 23 Apr 2019 13:57:15 +0530 [thread overview]
Message-ID: <20190423082730.370-2-vidyas@nvidia.com> (raw)
In-Reply-To: <20190423082730.370-1-vidyas@nvidia.com>
Add #defines only for the Data Link Feature and Physical Layer 16.0 GT/s
features.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
---
Changes from [v3]:
* None
Changes from [v2]:
* Updated commit message and description to explicitly mention that defines are
added only for some of the features and not all.
Changes from [v1]:
* None
include/uapi/linux/pci_regs.h | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index f7d3e7831fa8..4da04b1faab3 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -703,7 +703,9 @@
#define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */
#define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */
#define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */
-#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM
+#define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */
+#define PCI_EXT_CAP_ID_PL 0x26 /* Physical Layer 16.0 GT/s */
+#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL
#define PCI_EXT_CAP_DSN_SIZEOF 12
#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
@@ -1043,4 +1045,22 @@
#define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */
#define PCI_L1SS_CTL2 0x0c /* Control 2 Register */
+/* Data Link Feature */
+#define PCI_DLF_CAP 0x04 /* Capabilities Register */
+#define PCI_DLF_LOCAL_DLF_SUP_MASK 0x007fffff /* Local Data Link Feature Supported */
+#define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */
+#define PCI_DLF_STS 0x08 /* Status Register */
+#define PCI_DLF_REMOTE_DLF_SUP_MASK 0x007fffff /* Remote Data Link Feature Supported */
+#define PCI_DLF_REMOTE_DLF_SUP_VALID 0x80000000 /* Remote Data Link Feature Support Valid */
+
+/* Physical Layer 16.0 GT/s */
+#define PCI_PL_16GT_CAP 0x04 /* Capabilities Register */
+#define PCI_PL_16GT_CTRL 0x08 /* Control Register */
+#define PCI_PL_16GT_STS 0x0c /* Status Register */
+#define PCI_PL_16GT_LDPM_STS 0x10 /* Local Data Parity Mismatch Status Register */
+#define PCI_PL_16GT_FRDPM_STS 0x14 /* First Retimer Data Parity Mismatch Status Register */
+#define PCI_PL_16GT_SRDPM_STS 0x18 /* Second Retimer Data Parity Mismatch Status Register */
+#define PCI_PL_16GT_RSVD 0x1C /* Reserved */
+#define PCI_PL_16GT_LE_CTRL 0x20 /* Lane Equalization Control Register */
+
#endif /* LINUX_PCI_REGS_H */
--
2.17.1
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next prev parent reply other threads:[~2019-04-23 8:27 UTC|newest]
Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-23 8:27 [PATCH V4 00/16] Add Tegra194 PCIe support Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar [this message]
2019-04-23 8:27 ` [PATCH V4 01/16] PCI: Add #defines for some of PCIe spec r4.0 features Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar
2019-04-23 8:27 ` [PATCH V4 02/16] PCI/PME: Export pcie_pme_disable_msi() & pcie_pme_no_msi() APIs Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar
2019-04-23 8:27 ` [PATCH V4 03/16] PCI: Export pcie_bus_config symbol Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar
2019-04-23 8:27 ` [PATCH V4 04/16] PCI: dwc: Perform dbi regs write lock towards the end Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar
2019-04-23 8:27 ` [PATCH V4 05/16] PCI: dwc: Move config space capability search API Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar
2019-04-23 20:32 ` Bjorn Helgaas
2019-04-23 20:32 ` Bjorn Helgaas
2019-04-24 3:11 ` Vidya Sagar
2019-04-24 3:11 ` Vidya Sagar
2019-04-24 3:11 ` Vidya Sagar
2019-04-24 3:42 ` Oliver
2019-04-24 3:42 ` Oliver
2019-04-24 3:42 ` Oliver
2019-04-24 8:10 ` Gustavo Pimentel
2019-04-24 8:10 ` Gustavo Pimentel
2019-04-24 8:10 ` Gustavo Pimentel
2019-04-23 8:27 ` [PATCH V4 06/16] PCI: dwc: Add ext " Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar
2019-04-23 20:35 ` Bjorn Helgaas
2019-04-23 20:35 ` Bjorn Helgaas
2019-04-24 3:12 ` Vidya Sagar
2019-04-24 3:12 ` Vidya Sagar
2019-04-24 3:12 ` Vidya Sagar
2019-04-23 8:27 ` [PATCH V4 07/16] dt-bindings: PCI: designware: Add binding for CDM register check Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar
2019-04-23 8:27 ` [PATCH V4 08/16] PCI: dwc: Add support to enable " Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar
2019-04-23 8:27 ` [PATCH V4 09/16] Documentation/devicetree: Add PCIe supports-clkreq property Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar
2019-04-23 8:27 ` [PATCH V4 10/16] dt-bindings: PCI: tegra: Add device tree support for T194 Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar
2019-04-23 8:27 ` [PATCH V4 11/16] dt-bindings: PHY: P2U: Add Tegra 194 P2U block Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar
2019-04-23 8:27 ` [PATCH V4 12/16] arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar
2019-04-23 8:27 ` [PATCH V4 13/16] arm64: tegra: Enable PCIe slots in P2972-0000 board Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar
2019-04-23 8:27 ` [PATCH V4 14/16] phy: tegra: Add PCIe PIPE2UPHY support Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar
2019-04-23 8:27 ` [PATCH V4 15/16] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar
2019-04-23 8:27 ` [PATCH V4 16/16] arm64: Add Tegra194 PCIe driver to defconfig Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar
2019-04-23 8:27 ` Vidya Sagar
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