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From: Vidya Sagar <vidyas@nvidia.com>
To: lorenzo.pieralisi@arm.com, bhelgaas@google.com,
	robh+dt@kernel.org, mark.rutland@arm.com,
	thierry.reding@gmail.com, jonathanh@nvidia.com, kishon@ti.com,
	catalin.marinas@arm.com, will.deacon@arm.com,
	jingoohan1@gmail.com, gustavo.pimentel@synopsys.com
Cc: mperttunen@nvidia.com, linux-pci@vger.kernel.org,
	devicetree@vger.kernel.org, linux-tegra@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, kthota@nvidia.com,
	mmaddireddy@nvidia.com, vidyas@nvidia.com, sagar.tv@gmail.com
Subject: [PATCH V4 06/16] PCI: dwc: Add ext config space capability search API
Date: Tue, 23 Apr 2019 13:57:20 +0530	[thread overview]
Message-ID: <20190423082730.370-7-vidyas@nvidia.com> (raw)
In-Reply-To: <20190423082730.370-1-vidyas@nvidia.com>

Add extended configuration space capability search API using struct dw_pcie *
pointer

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
---
Changes from [v3]:
* None

Changes from [v2]:
* None

Changes from [v1]:
* This is a new patch in v2 series

 drivers/pci/controller/dwc/pcie-designware.c | 41 ++++++++++++++++++++
 drivers/pci/controller/dwc/pcie-designware.h |  1 +
 2 files changed, 42 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 6a98135244d6..ecf5fe8842f6 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -53,6 +53,47 @@ u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap)
 	return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
 }
 
+static int dw_pcie_find_next_ext_capability(struct dw_pcie *pci, int start,
+					    int cap)
+{
+	u32 header;
+	int ttl;
+	int pos = PCI_CFG_SPACE_SIZE;
+
+	/* minimum 8 bytes per capability */
+	ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
+
+	if (start)
+		pos = start;
+
+	header = dw_pcie_readl_dbi(pci, pos);
+	/*
+	 * If we have no capabilities, this is indicated by cap ID,
+	 * cap version and next pointer all being 0.
+	 */
+	if (header == 0)
+		return 0;
+
+	while (ttl-- > 0) {
+		if (PCI_EXT_CAP_ID(header) == cap && pos != start)
+			return pos;
+
+		pos = PCI_EXT_CAP_NEXT(header);
+		if (pos < PCI_CFG_SPACE_SIZE)
+			break;
+
+		header = dw_pcie_readl_dbi(pci, pos);
+	}
+
+	return 0;
+}
+
+int dw_pcie_find_ext_capability(struct dw_pcie *pci, int cap)
+{
+	return dw_pcie_find_next_ext_capability(pci, 0, cap);
+}
+EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability);
+
 int dw_pcie_read(void __iomem *addr, int size, u32 *val)
 {
 	if (!IS_ALIGNED((uintptr_t)addr, size)) {
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 35160b4ce929..67307842e003 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -249,6 +249,7 @@ struct dw_pcie {
 		container_of((endpoint), struct dw_pcie, ep)
 
 u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap);
+int dw_pcie_find_ext_capability(struct dw_pcie *pci, int cap);
 
 int dw_pcie_read(void __iomem *addr, int size, u32 *val);
 int dw_pcie_write(void __iomem *addr, int size, u32 val);
-- 
2.17.1

WARNING: multiple messages have this Message-ID (diff)
From: Vidya Sagar <vidyas@nvidia.com>
To: <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
	<robh+dt@kernel.org>, <mark.rutland@arm.com>,
	<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
	<kishon@ti.com>, <catalin.marinas@arm.com>, <will.deacon@arm.com>,
	<jingoohan1@gmail.com>, <gustavo.pimentel@synopsys.com>
Cc: <mperttunen@nvidia.com>, <linux-pci@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>, <kthota@nvidia.com>,
	<mmaddireddy@nvidia.com>, <vidyas@nvidia.com>,
	<sagar.tv@gmail.com>
Subject: [PATCH V4 06/16] PCI: dwc: Add ext config space capability search API
Date: Tue, 23 Apr 2019 13:57:20 +0530	[thread overview]
Message-ID: <20190423082730.370-7-vidyas@nvidia.com> (raw)
In-Reply-To: <20190423082730.370-1-vidyas@nvidia.com>

Add extended configuration space capability search API using struct dw_pcie *
pointer

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
---
Changes from [v3]:
* None

Changes from [v2]:
* None

Changes from [v1]:
* This is a new patch in v2 series

 drivers/pci/controller/dwc/pcie-designware.c | 41 ++++++++++++++++++++
 drivers/pci/controller/dwc/pcie-designware.h |  1 +
 2 files changed, 42 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 6a98135244d6..ecf5fe8842f6 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -53,6 +53,47 @@ u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap)
 	return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
 }
 
+static int dw_pcie_find_next_ext_capability(struct dw_pcie *pci, int start,
+					    int cap)
+{
+	u32 header;
+	int ttl;
+	int pos = PCI_CFG_SPACE_SIZE;
+
+	/* minimum 8 bytes per capability */
+	ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
+
+	if (start)
+		pos = start;
+
+	header = dw_pcie_readl_dbi(pci, pos);
+	/*
+	 * If we have no capabilities, this is indicated by cap ID,
+	 * cap version and next pointer all being 0.
+	 */
+	if (header == 0)
+		return 0;
+
+	while (ttl-- > 0) {
+		if (PCI_EXT_CAP_ID(header) == cap && pos != start)
+			return pos;
+
+		pos = PCI_EXT_CAP_NEXT(header);
+		if (pos < PCI_CFG_SPACE_SIZE)
+			break;
+
+		header = dw_pcie_readl_dbi(pci, pos);
+	}
+
+	return 0;
+}
+
+int dw_pcie_find_ext_capability(struct dw_pcie *pci, int cap)
+{
+	return dw_pcie_find_next_ext_capability(pci, 0, cap);
+}
+EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability);
+
 int dw_pcie_read(void __iomem *addr, int size, u32 *val)
 {
 	if (!IS_ALIGNED((uintptr_t)addr, size)) {
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 35160b4ce929..67307842e003 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -249,6 +249,7 @@ struct dw_pcie {
 		container_of((endpoint), struct dw_pcie, ep)
 
 u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap);
+int dw_pcie_find_ext_capability(struct dw_pcie *pci, int cap);
 
 int dw_pcie_read(void __iomem *addr, int size, u32 *val);
 int dw_pcie_write(void __iomem *addr, int size, u32 val);
-- 
2.17.1


WARNING: multiple messages have this Message-ID (diff)
From: Vidya Sagar <vidyas@nvidia.com>
To: <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
	<robh+dt@kernel.org>,  <mark.rutland@arm.com>,
	<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
	<kishon@ti.com>, <catalin.marinas@arm.com>, <will.deacon@arm.com>,
	<jingoohan1@gmail.com>, <gustavo.pimentel@synopsys.com>
Cc: devicetree@vger.kernel.org, mmaddireddy@nvidia.com,
	kthota@nvidia.com, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org, mperttunen@nvidia.com,
	linux-tegra@vger.kernel.org, vidyas@nvidia.com,
	linux-arm-kernel@lists.infradead.org, sagar.tv@gmail.com
Subject: [PATCH V4 06/16] PCI: dwc: Add ext config space capability search API
Date: Tue, 23 Apr 2019 13:57:20 +0530	[thread overview]
Message-ID: <20190423082730.370-7-vidyas@nvidia.com> (raw)
In-Reply-To: <20190423082730.370-1-vidyas@nvidia.com>

Add extended configuration space capability search API using struct dw_pcie *
pointer

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
---
Changes from [v3]:
* None

Changes from [v2]:
* None

Changes from [v1]:
* This is a new patch in v2 series

 drivers/pci/controller/dwc/pcie-designware.c | 41 ++++++++++++++++++++
 drivers/pci/controller/dwc/pcie-designware.h |  1 +
 2 files changed, 42 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 6a98135244d6..ecf5fe8842f6 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -53,6 +53,47 @@ u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap)
 	return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
 }
 
+static int dw_pcie_find_next_ext_capability(struct dw_pcie *pci, int start,
+					    int cap)
+{
+	u32 header;
+	int ttl;
+	int pos = PCI_CFG_SPACE_SIZE;
+
+	/* minimum 8 bytes per capability */
+	ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
+
+	if (start)
+		pos = start;
+
+	header = dw_pcie_readl_dbi(pci, pos);
+	/*
+	 * If we have no capabilities, this is indicated by cap ID,
+	 * cap version and next pointer all being 0.
+	 */
+	if (header == 0)
+		return 0;
+
+	while (ttl-- > 0) {
+		if (PCI_EXT_CAP_ID(header) == cap && pos != start)
+			return pos;
+
+		pos = PCI_EXT_CAP_NEXT(header);
+		if (pos < PCI_CFG_SPACE_SIZE)
+			break;
+
+		header = dw_pcie_readl_dbi(pci, pos);
+	}
+
+	return 0;
+}
+
+int dw_pcie_find_ext_capability(struct dw_pcie *pci, int cap)
+{
+	return dw_pcie_find_next_ext_capability(pci, 0, cap);
+}
+EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability);
+
 int dw_pcie_read(void __iomem *addr, int size, u32 *val)
 {
 	if (!IS_ALIGNED((uintptr_t)addr, size)) {
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 35160b4ce929..67307842e003 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -249,6 +249,7 @@ struct dw_pcie {
 		container_of((endpoint), struct dw_pcie, ep)
 
 u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap);
+int dw_pcie_find_ext_capability(struct dw_pcie *pci, int cap);
 
 int dw_pcie_read(void __iomem *addr, int size, u32 *val);
 int dw_pcie_write(void __iomem *addr, int size, u32 val);
-- 
2.17.1


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  parent reply	other threads:[~2019-04-23  8:27 UTC|newest]

Thread overview: 67+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-23  8:27 [PATCH V4 00/16] Add Tegra194 PCIe support Vidya Sagar
2019-04-23  8:27 ` Vidya Sagar
2019-04-23  8:27 ` Vidya Sagar
2019-04-23  8:27 ` [PATCH V4 01/16] PCI: Add #defines for some of PCIe spec r4.0 features Vidya Sagar
2019-04-23  8:27   ` Vidya Sagar
2019-04-23  8:27   ` Vidya Sagar
2019-04-23  8:27 ` [PATCH V4 02/16] PCI/PME: Export pcie_pme_disable_msi() & pcie_pme_no_msi() APIs Vidya Sagar
2019-04-23  8:27   ` Vidya Sagar
2019-04-23  8:27   ` Vidya Sagar
2019-04-23  8:27 ` [PATCH V4 03/16] PCI: Export pcie_bus_config symbol Vidya Sagar
2019-04-23  8:27   ` Vidya Sagar
2019-04-23  8:27   ` Vidya Sagar
2019-04-23  8:27 ` [PATCH V4 04/16] PCI: dwc: Perform dbi regs write lock towards the end Vidya Sagar
2019-04-23  8:27   ` Vidya Sagar
2019-04-23  8:27   ` Vidya Sagar
2019-04-23  8:27 ` [PATCH V4 05/16] PCI: dwc: Move config space capability search API Vidya Sagar
2019-04-23  8:27   ` Vidya Sagar
2019-04-23  8:27   ` Vidya Sagar
2019-04-23 20:32   ` Bjorn Helgaas
2019-04-23 20:32     ` Bjorn Helgaas
2019-04-24  3:11     ` Vidya Sagar
2019-04-24  3:11       ` Vidya Sagar
2019-04-24  3:11       ` Vidya Sagar
2019-04-24  3:42       ` Oliver
2019-04-24  3:42         ` Oliver
2019-04-24  3:42         ` Oliver
2019-04-24  8:10     ` Gustavo Pimentel
2019-04-24  8:10       ` Gustavo Pimentel
2019-04-24  8:10       ` Gustavo Pimentel
2019-04-23  8:27 ` Vidya Sagar [this message]
2019-04-23  8:27   ` [PATCH V4 06/16] PCI: dwc: Add ext " Vidya Sagar
2019-04-23  8:27   ` Vidya Sagar
2019-04-23 20:35   ` Bjorn Helgaas
2019-04-23 20:35     ` Bjorn Helgaas
2019-04-24  3:12     ` Vidya Sagar
2019-04-24  3:12       ` Vidya Sagar
2019-04-24  3:12       ` Vidya Sagar
2019-04-23  8:27 ` [PATCH V4 07/16] dt-bindings: PCI: designware: Add binding for CDM register check Vidya Sagar
2019-04-23  8:27   ` Vidya Sagar
2019-04-23  8:27   ` Vidya Sagar
2019-04-23  8:27 ` [PATCH V4 08/16] PCI: dwc: Add support to enable " Vidya Sagar
2019-04-23  8:27   ` Vidya Sagar
2019-04-23  8:27   ` Vidya Sagar
2019-04-23  8:27 ` [PATCH V4 09/16] Documentation/devicetree: Add PCIe supports-clkreq property Vidya Sagar
2019-04-23  8:27   ` Vidya Sagar
2019-04-23  8:27   ` Vidya Sagar
2019-04-23  8:27 ` [PATCH V4 10/16] dt-bindings: PCI: tegra: Add device tree support for T194 Vidya Sagar
2019-04-23  8:27   ` Vidya Sagar
2019-04-23  8:27   ` Vidya Sagar
2019-04-23  8:27 ` [PATCH V4 11/16] dt-bindings: PHY: P2U: Add Tegra 194 P2U block Vidya Sagar
2019-04-23  8:27   ` Vidya Sagar
2019-04-23  8:27   ` Vidya Sagar
2019-04-23  8:27 ` [PATCH V4 12/16] arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT Vidya Sagar
2019-04-23  8:27   ` Vidya Sagar
2019-04-23  8:27   ` Vidya Sagar
2019-04-23  8:27 ` [PATCH V4 13/16] arm64: tegra: Enable PCIe slots in P2972-0000 board Vidya Sagar
2019-04-23  8:27   ` Vidya Sagar
2019-04-23  8:27   ` Vidya Sagar
2019-04-23  8:27 ` [PATCH V4 14/16] phy: tegra: Add PCIe PIPE2UPHY support Vidya Sagar
2019-04-23  8:27   ` Vidya Sagar
2019-04-23  8:27   ` Vidya Sagar
2019-04-23  8:27 ` [PATCH V4 15/16] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
2019-04-23  8:27   ` Vidya Sagar
2019-04-23  8:27   ` Vidya Sagar
2019-04-23  8:27 ` [PATCH V4 16/16] arm64: Add Tegra194 PCIe driver to defconfig Vidya Sagar
2019-04-23  8:27   ` Vidya Sagar
2019-04-23  8:27   ` Vidya Sagar

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