[PATCH v2] drm/i915: Corrupt DSI picture fix for GeminiLake

[Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>]

Currently due to regression CI machine
displays show corrupt picture.
Problem is when CDCLK is as low as 79200, picture gets
unstable, while DSI and DE pll values were
confirmed to be correct.
Limiting to 158400 as agreed with Ville.

We could not come up with any better solution
yet, as PLL divider values both for MIPI(DSI PLL) and
CDCLK(DE PLL) are correct, however seems that due to some
boundary conditions, when clocking is too low we get
wrong timings for DSI display.
Similar workaround exists for VLV though, so just
took similar condition into use. At least that way
GLK platform will start to be usable again, with
current drm-tip.

v2: Fixed commit subject as suggested.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_cdclk.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index ae40a8679314..2b23f8500362 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -2277,6 +2277,15 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
 	    IS_VALLEYVIEW(dev_priv))
 		min_cdclk = max(320000, min_cdclk);
 
+	/*
+	 * On Geminilake once the CDCLK gets as low as 79200
+	 * picture gets unstable, despite that values are
+	 * correct for DSI PLL and DE PLL.
+	 */
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
+	    IS_GEMINILAKE(dev_priv))
+		min_cdclk = max(158400, min_cdclk);
+
 	if (min_cdclk > dev_priv->max_cdclk_freq) {
 		DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n",
 			      min_cdclk, dev_priv->max_cdclk_freq);
-- 
2.17.1

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