From: Chris Packham <chris.packham@alliedtelesis.co.nz> To: linux@armlinux.org.uk, bp@alien8.de, mark.rutland@arm.com, robh+dt@kernel.org, mchehab@kernel.org, james.morse@arm.com, jlu@pengutronix.de, gregory.clement@bootlin.com Cc: linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Packham <chris.packham@alliedtelesis.co.nz>, Rob Herring <robh@kernel.org> Subject: [PATCH v8 5/9] dt-bindings: ARM: document marvell,ecc-enable binding Date: Fri, 10 May 2019 22:15:32 +1200 [thread overview] Message-ID: <20190510101536.6724-6-chris.packham@alliedtelesis.co.nz> (raw) In-Reply-To: <20190510101536.6724-1-chris.packham@alliedtelesis.co.nz> Add documentation for the marvell,ecc-enable properties which can be used to enable ECC on the Marvell aurora cache. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Reviewed-by: Rob Herring <robh@kernel.org> --- Notes: Changes in v7: - remove marvell,ecc-disable Changes in v6: - new (split binding doc from implementation). Documentation/devicetree/bindings/arm/l2c2x0.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.yaml b/Documentation/devicetree/bindings/arm/l2c2x0.yaml index bfc5c185561c..913a8cd8b2c0 100644 --- a/Documentation/devicetree/bindings/arm/l2c2x0.yaml +++ b/Documentation/devicetree/bindings/arm/l2c2x0.yaml @@ -176,6 +176,10 @@ properties: description: disable parity checking on the L2 cache (L220 or PL310). type: boolean + marvell,ecc-enable: + description: enable ECC protection on the L2 cache + type: boolean + arm,outer-sync-disable: description: disable the outer sync operation on the L2 cache. Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that -- 2.21.0
WARNING: multiple messages have this Message-ID (diff)
From: Chris Packham <chris.packham@alliedtelesis.co.nz> To: linux@armlinux.org.uk, bp@alien8.de, mark.rutland@arm.com, robh+dt@kernel.org, mchehab@kernel.org, james.morse@arm.com, jlu@pengutronix.de, gregory.clement@bootlin.com Cc: Rob Herring <robh@kernel.org>, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Packham <chris.packham@alliedtelesis.co.nz>, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org Subject: [PATCH v8 5/9] dt-bindings: ARM: document marvell,ecc-enable binding Date: Fri, 10 May 2019 22:15:32 +1200 [thread overview] Message-ID: <20190510101536.6724-6-chris.packham@alliedtelesis.co.nz> (raw) In-Reply-To: <20190510101536.6724-1-chris.packham@alliedtelesis.co.nz> Add documentation for the marvell,ecc-enable properties which can be used to enable ECC on the Marvell aurora cache. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Reviewed-by: Rob Herring <robh@kernel.org> --- Notes: Changes in v7: - remove marvell,ecc-disable Changes in v6: - new (split binding doc from implementation). Documentation/devicetree/bindings/arm/l2c2x0.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.yaml b/Documentation/devicetree/bindings/arm/l2c2x0.yaml index bfc5c185561c..913a8cd8b2c0 100644 --- a/Documentation/devicetree/bindings/arm/l2c2x0.yaml +++ b/Documentation/devicetree/bindings/arm/l2c2x0.yaml @@ -176,6 +176,10 @@ properties: description: disable parity checking on the L2 cache (L220 or PL310). type: boolean + marvell,ecc-enable: + description: enable ECC protection on the L2 cache + type: boolean + arm,outer-sync-disable: description: disable the outer sync operation on the L2 cache. Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that -- 2.21.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-05-10 10:15 UTC|newest] Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-05-10 10:15 [PATCH v8 0/9] EDAC drivers for Armada XP L2 and DDR Chris Packham 2019-05-10 10:15 ` Chris Packham 2019-05-10 10:15 ` [PATCH v8 1/9] ARM: l2c: move cache-aurora-l2.h to asm/hardware Chris Packham 2019-05-10 10:15 ` Chris Packham 2019-05-10 10:15 ` [PATCH v8 2/9] ARM: aurora-l2: add prefix to MAX_RANGE_SIZE Chris Packham 2019-05-10 10:15 ` Chris Packham 2019-05-10 10:15 ` Chris Packham 2019-05-10 10:15 ` [PATCH v8 3/9] ARM: aurora-l2: add defines for parity and ECC registers Chris Packham 2019-05-10 10:15 ` Chris Packham 2019-05-10 10:15 ` [PATCH v8 4/9] ARM: l2x0: support parity-enable/disable on aurora Chris Packham 2019-05-10 10:15 ` Chris Packham 2019-05-10 10:15 ` Chris Packham [this message] 2019-05-10 10:15 ` [PATCH v8 5/9] dt-bindings: ARM: document marvell,ecc-enable binding Chris Packham 2019-05-10 10:15 ` [PATCH v8 6/9] ARM: l2x0: add marvell,ecc-enable property for aurora Chris Packham 2019-05-10 10:15 ` Chris Packham 2019-05-10 10:15 ` Chris Packham 2019-05-10 10:15 ` [PATCH v8 7/9] EDAC: Add missing debugfs_create_x32 wrapper Chris Packham 2019-05-10 10:15 ` Chris Packham 2019-05-10 10:15 ` [PATCH v8 8/9] EDAC: Add driver for the Marvell Armada XP SDRAM and L2 cache ECC Chris Packham 2019-05-10 10:15 ` Chris Packham 2019-05-10 10:15 ` [PATCH v8 9/9] EDAC: armada_xp: Add support for more SoCs Chris Packham 2019-05-10 10:15 ` Chris Packham 2019-06-07 0:47 ` [PATCH v8 0/9] EDAC drivers for Armada XP L2 and DDR Chris Packham 2019-06-07 0:47 ` Chris Packham 2019-06-07 0:47 ` Chris Packham
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