From: Julien Grall <julien.grall@arm.com> To: xen-devel@lists.xenproject.org Cc: Oleksandr_Tyshchenko@epam.com, Julien Grall <julien.grall@arm.com>, Stefano Stabellini <sstabellini@kernel.org>, Andrii_Anisov@epam.com Subject: [PATCH MM-PART2 RESEND v2 04/19] xen/arm: Rework HSCTLR_BASE Date: Tue, 14 May 2019 13:24:41 +0100 [thread overview] Message-ID: <20190514122456.28559-5-julien.grall@arm.com> (raw) In-Reply-To: <20190514122456.28559-1-julien.grall@arm.com> The current value of HSCTLR_BASE for Arm64 is pretty wrong. It would actually turn on SCTLR_EL2.nAA (bit 6) on hardware implementing ARMv8.4-LSE. Furthermore, the documentation of what is cleared/set in SCTLR_EL2 is also not correct and looks like to be a verbatim copy from Arm32. HSCTLR_BASE is replaced with a bunch of per-architecture new defines helping to understand better what is the initialie value for SCTLR_EL2/HSCTLR. Note the defines *_CLEAR are only used to check the state of each bits are known. Lastly, the documentation is dropped from arm{32,64}/head.S as it would be pretty easy to get out-of-sync with the definitions. Signed-off-by: Julien Grall <julien.grall@arm.com> --- Changes in v2: - Use BIT(..., UL) instead of _BITUL --- xen/arch/arm/arm32/head.S | 12 +-------- xen/arch/arm/arm64/head.S | 10 +------- xen/include/asm-arm/processor.h | 54 ++++++++++++++++++++++++++++++++++++++++- 3 files changed, 55 insertions(+), 21 deletions(-) diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index 454d24537c..8a98607459 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -234,17 +234,7 @@ cpu_init_done: ldr r0, =(TCR_RES1|TCR_SH0_IS|TCR_ORGN0_WBWA|TCR_IRGN0_WBWA|TCR_T0SZ(0)) mcr CP32(r0, HTCR) - /* - * Set up the HSCTLR: - * Exceptions in LE ARM, - * Low-latency IRQs disabled, - * Write-implies-XN disabled (for now), - * D-cache disabled (for now), - * I-cache enabled, - * Alignment checking enabled, - * MMU translation disabled (for now). - */ - ldr r0, =(HSCTLR_BASE|SCTLR_Axx_ELx_A) + ldr r0, =HSCTLR_SET mcr CP32(r0, HSCTLR) /* diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index 8a6be3352e..4fe904c51d 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -363,15 +363,7 @@ skip_bss: msr tcr_el2, x0 - /* Set up the SCTLR_EL2: - * Exceptions in LE ARM, - * Low-latency IRQs disabled, - * Write-implies-XN disabled (for now), - * D-cache disabled (for now), - * I-cache enabled, - * Alignment checking disabled, - * MMU translation disabled (for now). */ - ldr x0, =(HSCTLR_BASE) + ldr x0, =SCTLR_EL2_SET msr SCTLR_EL2, x0 /* Ensure that any exceptions encountered at EL2 diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index bbcba061ca..9afc3786c5 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -127,6 +127,9 @@ #define SCTLR_A32_ELx_TE BIT(30, UL) #define SCTLR_A32_ELx_FI BIT(21, UL) +/* Common bits for SCTLR_ELx for Arm64 */ +#define SCTLR_A64_ELx_SA BIT(3, UL) + /* Common bits for SCTLR_ELx on all architectures */ #define SCTLR_Axx_ELx_EE BIT(25, UL) #define SCTLR_Axx_ELx_WXN BIT(19, UL) @@ -135,7 +138,56 @@ #define SCTLR_Axx_ELx_A BIT(1, UL) #define SCTLR_Axx_ELx_M BIT(0, UL) -#define HSCTLR_BASE _AC(0x30c51878,U) +#ifdef CONFIG_ARM_32 + +#define HSCTLR_RES1 (BIT( 3, UL) | BIT( 4, UL) | BIT( 5, UL) |\ + BIT( 6, UL) | BIT(11, UL) | BIT(16, UL) |\ + BIT(18, UL) | BIT(22, UL) | BIT(23, UL) |\ + BIT(28, UL) | BIT(29, UL)) + +#define HSCTLR_RES0 (BIT(7, UL) | BIT(8, UL) | BIT(9, UL) | BIT(10, UL) |\ + BIT(13, UL) | BIT(14, UL) | BIT(15, UL) | BIT(17, UL) |\ + BIT(20, UL) | BIT(24, UL) | BIT(26, UL) | BIT(27, UL) |\ + BIT(31, UL)) + +/* Initial value for HSCTLR */ +#define HSCTLR_SET (HSCTLR_RES1 | SCTLR_Axx_ELx_A | SCTLR_Axx_ELx_I) + +#define HSCTLR_CLEAR (HSCTLR_RES0 | SCTLR_Axx_ELx_M |\ + SCTLR_Axx_ELx_C | SCTLR_Axx_ELx_WXN |\ + SCTLR_A32_ELx_FI | SCTLR_Axx_ELx_EE |\ + SCTLR_A32_ELx_TE) + +#if (HSCTLR_SET ^ HSCTLR_CLEAR) != 0xffffffffU +#error "Inconsistent HSCTLR set/clear bits" +#endif + +#else + +#define SCTLR_EL2_RES1 (BIT( 4, UL) | BIT( 5, UL) | BIT(11, UL) |\ + BIT(16, UL) | BIT(18, UL) | BIT(22, UL) |\ + BIT(23, UL) | BIT(28, UL) | BIT(29, UL)) + +#define SCTLR_EL2_RES0 (BIT( 6, UL) | BIT( 7, UL) | BIT( 8, UL) |\ + BIT( 9, UL) | BIT(10, UL) | BIT(13, UL) |\ + BIT(14, UL) | BIT(15, UL) | BIT(17, UL) |\ + BIT(20, UL) | BIT(21, UL) | BIT(24, UL) |\ + BIT(26, UL) | BIT(27, UL) | BIT(30, UL) |\ + BIT(31, UL) | (0xffffffffULL << 32)) + +/* Initial value for SCTLR_EL2 */ +#define SCTLR_EL2_SET (SCTLR_EL2_RES1 | SCTLR_A64_ELx_SA |\ + SCTLR_Axx_ELx_I) + +#define SCTLR_EL2_CLEAR (SCTLR_EL2_RES0 | SCTLR_Axx_ELx_M |\ + SCTLR_Axx_ELx_A | SCTLR_Axx_ELx_C |\ + SCTLR_Axx_ELx_WXN | SCTLR_Axx_ELx_EE) + +#if (SCTLR_EL2_SET ^ SCTLR_EL2_CLEAR) != 0xffffffffffffffffUL +#error "Inconsistent SCTLR_EL2 set/clear bits" +#endif + +#endif /* HCR Hyp Configuration Register */ #define HCR_RW (_AC(1,UL)<<31) /* Register Width, ARM64 only */ -- 2.11.0 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel
WARNING: multiple messages have this Message-ID (diff)
From: Julien Grall <julien.grall@arm.com> To: xen-devel@lists.xenproject.org Cc: Oleksandr_Tyshchenko@epam.com, Julien Grall <julien.grall@arm.com>, Stefano Stabellini <sstabellini@kernel.org>, Andrii_Anisov@epam.com Subject: [Xen-devel] [PATCH MM-PART2 RESEND v2 04/19] xen/arm: Rework HSCTLR_BASE Date: Tue, 14 May 2019 13:24:41 +0100 [thread overview] Message-ID: <20190514122456.28559-5-julien.grall@arm.com> (raw) Message-ID: <20190514122441.9Av9feOnYo7ysWnQbfVFjuemKz4hlD_PDFCtxwOGd6Y@z> (raw) In-Reply-To: <20190514122456.28559-1-julien.grall@arm.com> The current value of HSCTLR_BASE for Arm64 is pretty wrong. It would actually turn on SCTLR_EL2.nAA (bit 6) on hardware implementing ARMv8.4-LSE. Furthermore, the documentation of what is cleared/set in SCTLR_EL2 is also not correct and looks like to be a verbatim copy from Arm32. HSCTLR_BASE is replaced with a bunch of per-architecture new defines helping to understand better what is the initialie value for SCTLR_EL2/HSCTLR. Note the defines *_CLEAR are only used to check the state of each bits are known. Lastly, the documentation is dropped from arm{32,64}/head.S as it would be pretty easy to get out-of-sync with the definitions. Signed-off-by: Julien Grall <julien.grall@arm.com> --- Changes in v2: - Use BIT(..., UL) instead of _BITUL --- xen/arch/arm/arm32/head.S | 12 +-------- xen/arch/arm/arm64/head.S | 10 +------- xen/include/asm-arm/processor.h | 54 ++++++++++++++++++++++++++++++++++++++++- 3 files changed, 55 insertions(+), 21 deletions(-) diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index 454d24537c..8a98607459 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -234,17 +234,7 @@ cpu_init_done: ldr r0, =(TCR_RES1|TCR_SH0_IS|TCR_ORGN0_WBWA|TCR_IRGN0_WBWA|TCR_T0SZ(0)) mcr CP32(r0, HTCR) - /* - * Set up the HSCTLR: - * Exceptions in LE ARM, - * Low-latency IRQs disabled, - * Write-implies-XN disabled (for now), - * D-cache disabled (for now), - * I-cache enabled, - * Alignment checking enabled, - * MMU translation disabled (for now). - */ - ldr r0, =(HSCTLR_BASE|SCTLR_Axx_ELx_A) + ldr r0, =HSCTLR_SET mcr CP32(r0, HSCTLR) /* diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index 8a6be3352e..4fe904c51d 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -363,15 +363,7 @@ skip_bss: msr tcr_el2, x0 - /* Set up the SCTLR_EL2: - * Exceptions in LE ARM, - * Low-latency IRQs disabled, - * Write-implies-XN disabled (for now), - * D-cache disabled (for now), - * I-cache enabled, - * Alignment checking disabled, - * MMU translation disabled (for now). */ - ldr x0, =(HSCTLR_BASE) + ldr x0, =SCTLR_EL2_SET msr SCTLR_EL2, x0 /* Ensure that any exceptions encountered at EL2 diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index bbcba061ca..9afc3786c5 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -127,6 +127,9 @@ #define SCTLR_A32_ELx_TE BIT(30, UL) #define SCTLR_A32_ELx_FI BIT(21, UL) +/* Common bits for SCTLR_ELx for Arm64 */ +#define SCTLR_A64_ELx_SA BIT(3, UL) + /* Common bits for SCTLR_ELx on all architectures */ #define SCTLR_Axx_ELx_EE BIT(25, UL) #define SCTLR_Axx_ELx_WXN BIT(19, UL) @@ -135,7 +138,56 @@ #define SCTLR_Axx_ELx_A BIT(1, UL) #define SCTLR_Axx_ELx_M BIT(0, UL) -#define HSCTLR_BASE _AC(0x30c51878,U) +#ifdef CONFIG_ARM_32 + +#define HSCTLR_RES1 (BIT( 3, UL) | BIT( 4, UL) | BIT( 5, UL) |\ + BIT( 6, UL) | BIT(11, UL) | BIT(16, UL) |\ + BIT(18, UL) | BIT(22, UL) | BIT(23, UL) |\ + BIT(28, UL) | BIT(29, UL)) + +#define HSCTLR_RES0 (BIT(7, UL) | BIT(8, UL) | BIT(9, UL) | BIT(10, UL) |\ + BIT(13, UL) | BIT(14, UL) | BIT(15, UL) | BIT(17, UL) |\ + BIT(20, UL) | BIT(24, UL) | BIT(26, UL) | BIT(27, UL) |\ + BIT(31, UL)) + +/* Initial value for HSCTLR */ +#define HSCTLR_SET (HSCTLR_RES1 | SCTLR_Axx_ELx_A | SCTLR_Axx_ELx_I) + +#define HSCTLR_CLEAR (HSCTLR_RES0 | SCTLR_Axx_ELx_M |\ + SCTLR_Axx_ELx_C | SCTLR_Axx_ELx_WXN |\ + SCTLR_A32_ELx_FI | SCTLR_Axx_ELx_EE |\ + SCTLR_A32_ELx_TE) + +#if (HSCTLR_SET ^ HSCTLR_CLEAR) != 0xffffffffU +#error "Inconsistent HSCTLR set/clear bits" +#endif + +#else + +#define SCTLR_EL2_RES1 (BIT( 4, UL) | BIT( 5, UL) | BIT(11, UL) |\ + BIT(16, UL) | BIT(18, UL) | BIT(22, UL) |\ + BIT(23, UL) | BIT(28, UL) | BIT(29, UL)) + +#define SCTLR_EL2_RES0 (BIT( 6, UL) | BIT( 7, UL) | BIT( 8, UL) |\ + BIT( 9, UL) | BIT(10, UL) | BIT(13, UL) |\ + BIT(14, UL) | BIT(15, UL) | BIT(17, UL) |\ + BIT(20, UL) | BIT(21, UL) | BIT(24, UL) |\ + BIT(26, UL) | BIT(27, UL) | BIT(30, UL) |\ + BIT(31, UL) | (0xffffffffULL << 32)) + +/* Initial value for SCTLR_EL2 */ +#define SCTLR_EL2_SET (SCTLR_EL2_RES1 | SCTLR_A64_ELx_SA |\ + SCTLR_Axx_ELx_I) + +#define SCTLR_EL2_CLEAR (SCTLR_EL2_RES0 | SCTLR_Axx_ELx_M |\ + SCTLR_Axx_ELx_A | SCTLR_Axx_ELx_C |\ + SCTLR_Axx_ELx_WXN | SCTLR_Axx_ELx_EE) + +#if (SCTLR_EL2_SET ^ SCTLR_EL2_CLEAR) != 0xffffffffffffffffUL +#error "Inconsistent SCTLR_EL2 set/clear bits" +#endif + +#endif /* HCR Hyp Configuration Register */ #define HCR_RW (_AC(1,UL)<<31) /* Register Width, ARM64 only */ -- 2.11.0 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel
next prev parent reply other threads:[~2019-05-14 12:25 UTC|newest] Thread overview: 114+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-05-14 12:24 [PATCH MM-PART2 RESEND v2 00/19] xen/arm: Clean-up & fixes in boot/mm code Julien Grall 2019-05-14 12:24 ` [Xen-devel] " Julien Grall 2019-05-14 12:24 ` [PATCH MM-PART2 RESEND v2 01/19] xen/const: Extend the existing macro BIT to take a suffix in parameter Julien Grall 2019-05-14 12:24 ` [Xen-devel] " Julien Grall 2019-05-14 12:37 ` Jan Beulich 2019-05-14 12:37 ` [Xen-devel] " Jan Beulich 2019-05-20 21:43 ` Stefano Stabellini 2019-05-20 21:43 ` [Xen-devel] " Stefano Stabellini 2019-05-21 10:01 ` Andrii Anisov 2019-05-21 10:01 ` [Xen-devel] " Andrii Anisov 2019-05-14 12:24 ` [PATCH MM-PART2 RESEND v2 02/19] xen/arm: Rename SCTLR_* defines and remove unused one Julien Grall 2019-05-14 12:24 ` [Xen-devel] " Julien Grall 2019-05-20 21:46 ` Stefano Stabellini 2019-05-20 21:46 ` [Xen-devel] " Stefano Stabellini 2019-05-14 12:24 ` [PATCH MM-PART2 RESEND v2 03/19] xen/arm: processor: Use BIT(.., UL) instead of _AC(1, U) in SCTLR_ defines Julien Grall 2019-05-14 12:24 ` [Xen-devel] " Julien Grall 2019-05-20 21:48 ` Stefano Stabellini 2019-05-20 21:48 ` [Xen-devel] " Stefano Stabellini 2019-05-21 10:01 ` Andrii Anisov 2019-05-21 10:01 ` [Xen-devel] " Andrii Anisov 2019-05-14 12:24 ` Julien Grall [this message] 2019-05-14 12:24 ` [Xen-devel] [PATCH MM-PART2 RESEND v2 04/19] xen/arm: Rework HSCTLR_BASE Julien Grall 2019-05-20 22:56 ` Stefano Stabellini 2019-05-20 22:56 ` [Xen-devel] " Stefano Stabellini 2019-05-21 10:09 ` Julien Grall 2019-05-21 10:09 ` [Xen-devel] " Julien Grall 2019-05-29 16:54 ` Julien Grall 2019-05-29 16:54 ` [Xen-devel] " Julien Grall 2019-06-03 23:12 ` Stefano Stabellini 2019-06-03 23:12 ` [Xen-devel] " Stefano Stabellini 2019-06-04 10:27 ` Julien Grall 2019-06-04 17:41 ` Stefano Stabellini 2019-05-30 16:17 ` Andrii Anisov 2019-05-30 16:17 ` [Xen-devel] " Andrii Anisov 2019-05-14 12:24 ` [PATCH MM-PART2 RESEND v2 05/19] xen/arm: Remove parameter cpuid from start_xen Julien Grall 2019-05-14 12:24 ` [Xen-devel] " Julien Grall 2019-05-21 10:01 ` Andrii Anisov 2019-05-21 10:01 ` [Xen-devel] " Andrii Anisov 2019-06-06 17:15 ` Julien Grall 2019-06-07 22:39 ` Stefano Stabellini 2019-05-14 12:24 ` [PATCH MM-PART2 RESEND v2 06/19] xen/arm: Rework secondary_start prototype Julien Grall 2019-05-14 12:24 ` [Xen-devel] " Julien Grall 2019-05-20 22:56 ` Stefano Stabellini 2019-05-20 22:56 ` [Xen-devel] " Stefano Stabellini 2019-05-29 17:06 ` Julien Grall 2019-05-29 17:06 ` [Xen-devel] " Julien Grall 2019-05-30 16:18 ` Andrii Anisov 2019-05-30 16:18 ` [Xen-devel] " Andrii Anisov 2019-05-14 12:24 ` [PATCH MM-PART2 RESEND v2 07/19] xen/arm64: head: Remove unnecessary comment Julien Grall 2019-05-14 12:24 ` [Xen-devel] " Julien Grall 2019-05-20 22:56 ` Stefano Stabellini 2019-05-20 22:56 ` [Xen-devel] " Stefano Stabellini 2019-05-14 12:24 ` [PATCH MM-PART2 RESEND v2 08/19] xen/arm64: head: Move earlyprintk messages in .rodata.str Julien Grall 2019-05-14 12:24 ` [Xen-devel] " Julien Grall 2019-05-20 22:56 ` Stefano Stabellini 2019-05-20 22:56 ` [Xen-devel] " Stefano Stabellini 2019-05-14 12:24 ` [PATCH MM-PART2 RESEND v2 09/19] xen/arm64: head: Correctly report the HW CPU ID Julien Grall 2019-05-14 12:24 ` [Xen-devel] " Julien Grall 2019-05-20 22:56 ` Stefano Stabellini 2019-05-20 22:56 ` [Xen-devel] " Stefano Stabellini 2019-05-14 12:24 ` [PATCH MM-PART2 RESEND v2 10/19] xen/arm32: " Julien Grall 2019-05-14 12:24 ` [Xen-devel] " Julien Grall 2019-06-03 22:45 ` Stefano Stabellini 2019-06-03 22:45 ` [Xen-devel] " Stefano Stabellini 2019-05-14 12:24 ` [PATCH MM-PART2 RESEND v2 11/19] xen/arm32: head: Don't set MAIR0 and MAIR1 Julien Grall 2019-05-14 12:24 ` [Xen-devel] " Julien Grall 2019-06-03 22:47 ` Stefano Stabellini 2019-06-03 22:47 ` [Xen-devel] " Stefano Stabellini 2019-05-14 12:24 ` [PATCH MM-PART2 RESEND v2 12/19] xen/arm32: head: Always zero r3 before update a page-table entry Julien Grall 2019-05-14 12:24 ` [Xen-devel] " Julien Grall 2019-05-21 10:03 ` Andrii Anisov 2019-05-21 10:03 ` [Xen-devel] " Andrii Anisov 2019-06-03 23:15 ` Stefano Stabellini 2019-06-03 23:15 ` [Xen-devel] " Stefano Stabellini 2019-05-14 12:24 ` [PATCH MM-PART2 RESEND v2 13/19] xen/arm32: mm: Avoid to zero and clean cache for CPU0 domheap Julien Grall 2019-05-14 12:24 ` [Xen-devel] " Julien Grall 2019-06-03 23:20 ` Stefano Stabellini 2019-06-03 23:20 ` [Xen-devel] " Stefano Stabellini 2019-05-14 12:24 ` [PATCH MM-PART2 RESEND v2 14/19] xen/arm32: mm: Avoid cleaning the cache for secondary CPUs page-tables Julien Grall 2019-05-14 12:24 ` [Xen-devel] " Julien Grall 2019-06-04 23:11 ` Stefano Stabellini 2019-06-05 10:19 ` Julien Grall 2019-06-10 10:15 ` Julien Grall 2019-06-10 20:28 ` Stefano Stabellini 2019-06-10 20:40 ` Julien Grall 2019-06-10 20:54 ` Stefano Stabellini 2019-05-14 12:24 ` [PATCH MM-PART2 RESEND v2 15/19] xen/arm: mm: Introduce DEFINE_PAGE_TABLE{, S} and use it Julien Grall 2019-05-14 12:24 ` [Xen-devel] " Julien Grall 2019-06-03 23:29 ` Stefano Stabellini 2019-06-03 23:29 ` [Xen-devel] " Stefano Stabellini 2019-05-14 12:24 ` [PATCH MM-PART2 RESEND v2 16/19] xen/arm: mm: Protect Xen page-table update with a spinlock Julien Grall 2019-05-14 12:24 ` [Xen-devel] " Julien Grall 2019-05-21 10:04 ` Andrii Anisov 2019-05-21 10:04 ` [Xen-devel] " Andrii Anisov 2019-06-04 23:11 ` Stefano Stabellini 2019-06-05 10:36 ` Julien Grall 2019-06-08 0:17 ` Stefano Stabellini 2019-06-13 12:06 ` Julien Grall 2019-05-14 12:24 ` [PATCH MM-PART2 RESEND v2 17/19] xen/arm: mm: Initialize page-tables earlier Julien Grall 2019-05-14 12:24 ` [Xen-devel] " Julien Grall 2019-06-04 23:12 ` Stefano Stabellini 2019-06-06 17:32 ` Julien Grall 2019-05-14 12:24 ` [PATCH MM-PART2 RESEND v2 18/19] xen/arm: mm: Check start is always before end in {destroy, modify}_xen_mappings Julien Grall 2019-05-14 12:24 ` [Xen-devel] " Julien Grall 2019-06-04 23:12 ` Stefano Stabellini 2019-05-14 12:24 ` [PATCH MM-PART2 RESEND v2 19/19] xen/arm: Pair call to set_fixmap with call to clear_fixmap in copy_from_paddr Julien Grall 2019-05-14 12:24 ` [Xen-devel] " Julien Grall 2019-06-04 17:59 ` Stefano Stabellini 2019-06-04 20:18 ` Julien Grall 2019-06-04 23:12 ` Stefano Stabellini 2019-06-06 17:38 ` Julien Grall 2019-05-29 17:23 ` [PATCH MM-PART2 RESEND v2 00/19] xen/arm: Clean-up & fixes in boot/mm code Julien Grall 2019-05-29 17:23 ` [Xen-devel] " Julien Grall 2019-06-13 12:09 ` Julien Grall
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