From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> To: igt-dev@lists.freedesktop.org Cc: Intel-gfx@lists.freedesktop.org Subject: [PATCH i-g-t 22/27] tests/i915_query: Engine discovery tests Date: Mon, 20 May 2019 15:47:34 +0100 [thread overview] Message-ID: <20190520144739.13111-23-tvrtko.ursulin@linux.intel.com> (raw) In-Reply-To: <20190520144739.13111-1-tvrtko.ursulin@linux.intel.com> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Test the new engine discovery query. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> --- tests/i915/i915_query.c | 247 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 247 insertions(+) diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c index 7d0c0e3a061c..ecbec3ae141d 100644 --- a/tests/i915/i915_query.c +++ b/tests/i915/i915_query.c @@ -483,6 +483,241 @@ test_query_topology_known_pci_ids(int fd, int devid) free(topo_info); } +static bool query_engine_info_supported(int fd) +{ + struct drm_i915_query_item item = { + .query_id = DRM_I915_QUERY_ENGINE_INFO, + }; + + return __i915_query_items(fd, &item, 1) == 0 && item.length > 0; +} + +static void engines_invalid(int fd) +{ + struct drm_i915_query_engine_info *engines; + struct drm_i915_query_item item; + unsigned int len; + + /* Flags is MBZ. */ + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.flags = 1; + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EINVAL); + + /* Length not zero and not greater or equal required size. */ + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = 1; + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EINVAL); + + /* Query correct length. */ + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + i915_query_items(fd, &item, 1); + igt_assert(item.length >= 0); + len = item.length; + + engines = malloc(len); + igt_assert(engines); + + /* Ivalid pointer. */ + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EFAULT); + + /* All fields in engines query are MBZ and only filled by the kernel. */ + + memset(engines, 0, len); + engines->num_engines = 1; + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EINVAL); + + memset(engines, 0, len); + engines->rsvd[0] = 1; + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EINVAL); + + memset(engines, 0, len); + engines->rsvd[1] = 1; + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EINVAL); + + memset(engines, 0, len); + engines->rsvd[2] = 1; + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EINVAL); + + free(engines); + + igt_assert(len <= 4096); + engines = mmap(0, 4096, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON, + -1, 0); + igt_assert(engines != MAP_FAILED); + + /* PROT_NONE is similar to unmapped area. */ + memset(engines, 0, len); + igt_assert_eq(mprotect(engines, len, PROT_NONE), 0); + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EFAULT); + igt_assert_eq(mprotect(engines, len, PROT_WRITE), 0); + + /* Read-only so kernel cannot fill the data back. */ + memset(engines, 0, len); + igt_assert_eq(mprotect(engines, len, PROT_READ), 0); + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EFAULT); + + munmap(engines, 4096); +} + +static bool +has_engine(struct drm_i915_query_engine_info *engines, + unsigned class, unsigned instance) +{ + unsigned int i; + + for (i = 0; i < engines->num_engines; i++) { + struct drm_i915_engine_info *engine = + (struct drm_i915_engine_info *)&engines->engines[i]; + + if (engine->engine.engine_class == class && + engine->engine.engine_instance == instance) + return true; + } + + return false; +} + +static void engines(int fd) +{ + struct drm_i915_query_engine_info *engines; + struct drm_i915_query_item item; + unsigned int len, i; + + engines = malloc(4096); + igt_assert(engines); + + /* Query required buffer length. */ + memset(engines, 0, 4096); + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert(item.length >= 0); + igt_assert(item.length <= 4096); + len = item.length; + + /* Check length larger than required works and reports same length. */ + memset(engines, 0, 4096); + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = 4096; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, len); + + /* Actual query. */ + memset(engines, 0, 4096); + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, len); + + /* Every GPU has at least one engine. */ + igt_assert(engines->num_engines > 0); + + /* MBZ fields. */ + igt_assert_eq(engines->rsvd[0], 0); + igt_assert_eq(engines->rsvd[1], 0); + igt_assert_eq(engines->rsvd[2], 0); + + /* Check results match the legacy GET_PARAM (where we can). */ + for (i = 0; i < engines->num_engines; i++) { + struct drm_i915_engine_info *engine = + (struct drm_i915_engine_info *)&engines->engines[i]; + + igt_debug("%u: class=%u instance=%u flags=%llx capabilities=%llx\n", + i, + engine->engine.engine_class, + engine->engine.engine_instance, + engine->flags, + engine->capabilities); + + /* MBZ fields. */ + igt_assert_eq(engine->rsvd0, 0); + igt_assert_eq(engine->rsvd1[0], 0); + igt_assert_eq(engine->rsvd1[1], 0); + + switch (engine->engine.engine_class) { + case I915_ENGINE_CLASS_RENDER: + /* Will be tested later. */ + break; + case I915_ENGINE_CLASS_COPY: + igt_assert(gem_has_blt(fd)); + break; + case I915_ENGINE_CLASS_VIDEO: + switch (engine->engine.engine_instance) { + case 0: + igt_assert(gem_has_bsd(fd)); + break; + case 1: + igt_assert(gem_has_bsd2(fd)); + break; + } + break; + case I915_ENGINE_CLASS_VIDEO_ENHANCE: + igt_assert(gem_has_vebox(fd)); + break; + default: + igt_assert(0); + } + } + + /* Reverse check to the above - all GET_PARAM engines are present. */ + igt_assert(has_engine(engines, I915_ENGINE_CLASS_RENDER, 0)); + if (gem_has_blt(fd)) + igt_assert(has_engine(engines, I915_ENGINE_CLASS_COPY, 0)); + if (gem_has_bsd(fd)) + igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO, 0)); + if (gem_has_bsd2(fd)) + igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO, 1)); + if (gem_has_vebox(fd)) + igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO_ENHANCE, + 0)); + + free(engines); +} + igt_main { int fd = -1; @@ -530,6 +765,18 @@ igt_main test_query_topology_known_pci_ids(fd, devid); } + igt_subtest_group { + igt_fixture { + igt_require(query_engine_info_supported(fd)); + } + + igt_subtest("engine-info-invalid") + engines_invalid(fd); + + igt_subtest("engine-info") + engines(fd); + } + igt_fixture { close(fd); } -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
WARNING: multiple messages have this Message-ID (diff)
From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> To: igt-dev@lists.freedesktop.org Cc: Intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH i-g-t 22/27] tests/i915_query: Engine discovery tests Date: Mon, 20 May 2019 15:47:34 +0100 [thread overview] Message-ID: <20190520144739.13111-23-tvrtko.ursulin@linux.intel.com> (raw) In-Reply-To: <20190520144739.13111-1-tvrtko.ursulin@linux.intel.com> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Test the new engine discovery query. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> --- tests/i915/i915_query.c | 247 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 247 insertions(+) diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c index 7d0c0e3a061c..ecbec3ae141d 100644 --- a/tests/i915/i915_query.c +++ b/tests/i915/i915_query.c @@ -483,6 +483,241 @@ test_query_topology_known_pci_ids(int fd, int devid) free(topo_info); } +static bool query_engine_info_supported(int fd) +{ + struct drm_i915_query_item item = { + .query_id = DRM_I915_QUERY_ENGINE_INFO, + }; + + return __i915_query_items(fd, &item, 1) == 0 && item.length > 0; +} + +static void engines_invalid(int fd) +{ + struct drm_i915_query_engine_info *engines; + struct drm_i915_query_item item; + unsigned int len; + + /* Flags is MBZ. */ + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.flags = 1; + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EINVAL); + + /* Length not zero and not greater or equal required size. */ + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = 1; + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EINVAL); + + /* Query correct length. */ + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + i915_query_items(fd, &item, 1); + igt_assert(item.length >= 0); + len = item.length; + + engines = malloc(len); + igt_assert(engines); + + /* Ivalid pointer. */ + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EFAULT); + + /* All fields in engines query are MBZ and only filled by the kernel. */ + + memset(engines, 0, len); + engines->num_engines = 1; + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EINVAL); + + memset(engines, 0, len); + engines->rsvd[0] = 1; + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EINVAL); + + memset(engines, 0, len); + engines->rsvd[1] = 1; + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EINVAL); + + memset(engines, 0, len); + engines->rsvd[2] = 1; + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EINVAL); + + free(engines); + + igt_assert(len <= 4096); + engines = mmap(0, 4096, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON, + -1, 0); + igt_assert(engines != MAP_FAILED); + + /* PROT_NONE is similar to unmapped area. */ + memset(engines, 0, len); + igt_assert_eq(mprotect(engines, len, PROT_NONE), 0); + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EFAULT); + igt_assert_eq(mprotect(engines, len, PROT_WRITE), 0); + + /* Read-only so kernel cannot fill the data back. */ + memset(engines, 0, len); + igt_assert_eq(mprotect(engines, len, PROT_READ), 0); + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EFAULT); + + munmap(engines, 4096); +} + +static bool +has_engine(struct drm_i915_query_engine_info *engines, + unsigned class, unsigned instance) +{ + unsigned int i; + + for (i = 0; i < engines->num_engines; i++) { + struct drm_i915_engine_info *engine = + (struct drm_i915_engine_info *)&engines->engines[i]; + + if (engine->engine.engine_class == class && + engine->engine.engine_instance == instance) + return true; + } + + return false; +} + +static void engines(int fd) +{ + struct drm_i915_query_engine_info *engines; + struct drm_i915_query_item item; + unsigned int len, i; + + engines = malloc(4096); + igt_assert(engines); + + /* Query required buffer length. */ + memset(engines, 0, 4096); + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert(item.length >= 0); + igt_assert(item.length <= 4096); + len = item.length; + + /* Check length larger than required works and reports same length. */ + memset(engines, 0, 4096); + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = 4096; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, len); + + /* Actual query. */ + memset(engines, 0, 4096); + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, len); + + /* Every GPU has at least one engine. */ + igt_assert(engines->num_engines > 0); + + /* MBZ fields. */ + igt_assert_eq(engines->rsvd[0], 0); + igt_assert_eq(engines->rsvd[1], 0); + igt_assert_eq(engines->rsvd[2], 0); + + /* Check results match the legacy GET_PARAM (where we can). */ + for (i = 0; i < engines->num_engines; i++) { + struct drm_i915_engine_info *engine = + (struct drm_i915_engine_info *)&engines->engines[i]; + + igt_debug("%u: class=%u instance=%u flags=%llx capabilities=%llx\n", + i, + engine->engine.engine_class, + engine->engine.engine_instance, + engine->flags, + engine->capabilities); + + /* MBZ fields. */ + igt_assert_eq(engine->rsvd0, 0); + igt_assert_eq(engine->rsvd1[0], 0); + igt_assert_eq(engine->rsvd1[1], 0); + + switch (engine->engine.engine_class) { + case I915_ENGINE_CLASS_RENDER: + /* Will be tested later. */ + break; + case I915_ENGINE_CLASS_COPY: + igt_assert(gem_has_blt(fd)); + break; + case I915_ENGINE_CLASS_VIDEO: + switch (engine->engine.engine_instance) { + case 0: + igt_assert(gem_has_bsd(fd)); + break; + case 1: + igt_assert(gem_has_bsd2(fd)); + break; + } + break; + case I915_ENGINE_CLASS_VIDEO_ENHANCE: + igt_assert(gem_has_vebox(fd)); + break; + default: + igt_assert(0); + } + } + + /* Reverse check to the above - all GET_PARAM engines are present. */ + igt_assert(has_engine(engines, I915_ENGINE_CLASS_RENDER, 0)); + if (gem_has_blt(fd)) + igt_assert(has_engine(engines, I915_ENGINE_CLASS_COPY, 0)); + if (gem_has_bsd(fd)) + igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO, 0)); + if (gem_has_bsd2(fd)) + igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO, 1)); + if (gem_has_vebox(fd)) + igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO_ENHANCE, + 0)); + + free(engines); +} + igt_main { int fd = -1; @@ -530,6 +765,18 @@ igt_main test_query_topology_known_pci_ids(fd, devid); } + igt_subtest_group { + igt_fixture { + igt_require(query_engine_info_supported(fd)); + } + + igt_subtest("engine-info-invalid") + engines_invalid(fd); + + igt_subtest("engine-info") + engines(fd); + } + igt_fixture { close(fd); } -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-05-20 14:47 UTC|newest] Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-05-20 14:47 [PATCH i-g-t 00/27] Media scalability tooling Tvrtko Ursulin 2019-05-20 14:47 ` [igt-dev] " Tvrtko Ursulin 2019-05-20 14:47 ` [PATCH i-g-t 01/27] scripts/trace.pl: Fix after intel_engine_notify removal Tvrtko Ursulin 2019-05-20 14:47 ` [igt-dev] " Tvrtko Ursulin 2019-05-20 14:47 ` [PATCH i-g-t 02/27] trace.pl: Ignore signaling on non i915 fences Tvrtko Ursulin 2019-05-20 14:47 ` [igt-dev] " Tvrtko Ursulin 2019-05-21 7:57 ` Chris Wilson 2019-05-21 7:57 ` Chris Wilson 2019-05-21 13:22 ` Tvrtko Ursulin 2019-05-21 13:22 ` Tvrtko Ursulin 2019-05-21 15:29 ` Chris Wilson 2019-05-21 15:29 ` Chris Wilson 2019-05-20 14:47 ` [PATCH i-g-t 03/27] headers: bump Tvrtko Ursulin 2019-05-20 14:47 ` [igt-dev] " Tvrtko Ursulin 2019-05-20 14:47 ` [PATCH i-g-t 04/27] trace.pl: Virtual engine support Tvrtko Ursulin 2019-05-20 14:47 ` [igt-dev] " Tvrtko Ursulin 2019-05-20 14:47 ` [PATCH i-g-t 05/27] trace.pl: Virtual engine preemption support Tvrtko Ursulin 2019-05-20 14:47 ` [igt-dev] " Tvrtko Ursulin 2019-05-20 14:47 ` [PATCH i-g-t 06/27] wsim/media-bench: i915 balancing Tvrtko Ursulin 2019-05-20 14:47 ` [Intel-gfx] " Tvrtko Ursulin 2019-05-20 14:47 ` [PATCH i-g-t 07/27] gem_wsim: Use IGT uapi headers Tvrtko Ursulin 2019-05-20 14:47 ` [igt-dev] " Tvrtko Ursulin 2019-05-20 14:47 ` [PATCH i-g-t 08/27] gem_wsim: Factor out common error handling Tvrtko Ursulin 2019-05-20 14:47 ` [igt-dev] " Tvrtko Ursulin 2019-05-20 14:47 ` [PATCH i-g-t 09/27] gem_wsim: More wsim_err Tvrtko Ursulin 2019-05-20 14:47 ` [igt-dev] " Tvrtko Ursulin 2019-05-20 14:47 ` [PATCH i-g-t 10/27] gem_wsim: Submit fence support Tvrtko Ursulin 2019-05-20 14:47 ` [igt-dev] " Tvrtko Ursulin 2019-05-20 14:47 ` [PATCH i-g-t 11/27] gem_wsim: Extract str to engine lookup Tvrtko Ursulin 2019-05-20 14:47 ` [igt-dev] " Tvrtko Ursulin 2019-05-20 14:47 ` [PATCH i-g-t 12/27] gem_wsim: Engine map support Tvrtko Ursulin 2019-05-20 14:47 ` [igt-dev] " Tvrtko Ursulin 2019-05-21 8:14 ` Chris Wilson 2019-05-21 8:14 ` Chris Wilson 2019-05-21 8:29 ` Tvrtko Ursulin 2019-05-21 8:29 ` Tvrtko Ursulin 2019-05-20 14:47 ` [PATCH i-g-t 13/27] gem_wsim: Save some lines by changing to implicit NULL checking Tvrtko Ursulin 2019-05-20 14:47 ` [igt-dev] " Tvrtko Ursulin 2019-05-20 14:47 ` [PATCH i-g-t 14/27] gem_wsim: Compact int command parsing with a macro Tvrtko Ursulin 2019-05-20 14:47 ` [igt-dev] " Tvrtko Ursulin 2019-05-20 14:47 ` [PATCH i-g-t 15/27] gem_wsim: Engine map load balance command Tvrtko Ursulin 2019-05-20 14:47 ` [igt-dev] " Tvrtko Ursulin 2019-05-20 14:47 ` [PATCH i-g-t 16/27] gem_wsim: Engine bond command Tvrtko Ursulin 2019-05-20 14:47 ` [igt-dev] " Tvrtko Ursulin 2019-05-20 14:47 ` [PATCH i-g-t 17/27] gem_wsim: Some more example workloads Tvrtko Ursulin 2019-05-20 14:47 ` [Intel-gfx] " Tvrtko Ursulin 2019-05-20 14:47 ` [PATCH i-g-t 18/27] gem_wsim: Infinite batch support Tvrtko Ursulin 2019-05-20 14:47 ` [igt-dev] " Tvrtko Ursulin 2019-05-20 14:47 ` [PATCH i-g-t 19/27] gem_wsim: Command line switch for specifying low slice count workloads Tvrtko Ursulin 2019-05-20 14:47 ` [Intel-gfx] " Tvrtko Ursulin 2019-05-20 14:47 ` [PATCH i-g-t 20/27] gem_wsim: Per context SSEU control Tvrtko Ursulin 2019-05-20 14:47 ` [igt-dev] " Tvrtko Ursulin 2019-05-20 14:47 ` [PATCH i-g-t 21/27] gem_wsim: Allow RCS virtual engine with " Tvrtko Ursulin 2019-05-20 14:47 ` [igt-dev] " Tvrtko Ursulin 2019-05-20 14:47 ` Tvrtko Ursulin [this message] 2019-05-20 14:47 ` [Intel-gfx] [PATCH i-g-t 22/27] tests/i915_query: Engine discovery tests Tvrtko Ursulin 2019-05-22 8:23 ` [igt-dev] " Andi Shyti 2019-05-22 8:23 ` Andi Shyti 2019-05-20 14:47 ` [PATCH i-g-t 23/27] gem_wsim: Consolidate engine assignments into helpers Tvrtko Ursulin 2019-05-20 14:47 ` [igt-dev] " Tvrtko Ursulin 2019-05-20 14:47 ` [PATCH i-g-t 24/27] gem_wsim: Discover engines Tvrtko Ursulin 2019-05-20 14:47 ` [igt-dev] " Tvrtko Ursulin 2019-05-21 13:54 ` Andi Shyti 2019-05-21 13:54 ` Andi Shyti 2019-05-20 14:47 ` [PATCH i-g-t 25/27] gem_wsim: Support Icelake parts Tvrtko Ursulin 2019-05-20 14:47 ` [igt-dev] " Tvrtko Ursulin 2019-05-20 14:47 ` [PATCH i-g-t 26/27] gem_wsim: Fix prng usage Tvrtko Ursulin 2019-05-20 14:47 ` [igt-dev] " Tvrtko Ursulin 2019-05-20 14:47 ` [PATCH i-g-t 27/27] gem_wsim: Allow random seed control Tvrtko Ursulin 2019-05-20 14:47 ` [igt-dev] " Tvrtko Ursulin 2019-05-21 9:22 ` [igt-dev] ✓ Fi.CI.BAT: success for Media scalability tooling (rev6) Patchwork 2019-05-21 13:10 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
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