From: Palmer Dabbelt <palmer@sifive.com> To: Peter Maydell <peter.maydell@linaro.org> Cc: Alistair Francis <alistair.francis@wdc.com>, Palmer Dabbelt <palmer@sifive.com>, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Igor Mammedov <imammedo@redhat.com> Subject: [Qemu-devel] [PULL 18/29] riscv: spike: Add a generic spike machine Date: Sat, 25 May 2019 18:09:37 -0700 [thread overview] Message-ID: <20190526010948.3923-19-palmer@sifive.com> (raw) In-Reply-To: <20190526010948.3923-1-palmer@sifive.com> From: Alistair Francis <Alistair.Francis@wdc.com> Add a generic spike machine (not tied to a version) and deprecate the spike mahines that are tied to a specific version. As we can now specify the CPU via the command line we no londer need specific versions of the spike machines. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> --- hw/riscv/spike.c | 106 ++++++++++++++++++++++++++++++++++++++++++- qemu-deprecated.texi | 6 +++ 2 files changed, 111 insertions(+), 1 deletion(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 2a000a58009a..5b33d4be3bbc 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -39,6 +39,7 @@ #include "chardev/char.h" #include "sysemu/arch_init.h" #include "sysemu/device_tree.h" +#include "sysemu/qtest.h" #include "exec/address-spaces.h" #include "elf.h" @@ -160,7 +161,89 @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap, qemu_fdt_add_subnode(fdt, "/chosen"); qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); } - } +} + +static void spike_board_init(MachineState *machine) +{ + const struct MemmapEntry *memmap = spike_memmap; + + SpikeState *s = g_new0(SpikeState, 1); + MemoryRegion *system_memory = get_system_memory(); + MemoryRegion *main_mem = g_new(MemoryRegion, 1); + MemoryRegion *mask_rom = g_new(MemoryRegion, 1); + int i; + + /* Initialize SOC */ + object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), + TYPE_RISCV_HART_ARRAY, &error_abort, NULL); + object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type", + &error_abort); + object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", + &error_abort); + object_property_set_bool(OBJECT(&s->soc), true, "realized", + &error_abort); + + /* register system main memory (actual RAM) */ + memory_region_init_ram(main_mem, NULL, "riscv.spike.ram", + machine->ram_size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base, + main_mem); + + /* create device tree */ + create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); + + /* boot rom */ + memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom", + memmap[SPIKE_MROM].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, + mask_rom); + + if (machine->kernel_filename) { + load_kernel(machine->kernel_filename); + } + + /* reset vector */ + uint32_t reset_vec[8] = { + 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ + 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ + 0xf1402573, /* csrr a0, mhartid */ +#if defined(TARGET_RISCV32) + 0x0182a283, /* lw t0, 24(t0) */ +#elif defined(TARGET_RISCV64) + 0x0182b283, /* ld t0, 24(t0) */ +#endif + 0x00028067, /* jr t0 */ + 0x00000000, + memmap[SPIKE_DRAM].base, /* start: .dword DRAM_BASE */ + 0x00000000, + /* dtb: */ + }; + + /* copy in the reset vector in little_endian byte order */ + for (i = 0; i < sizeof(reset_vec) >> 2; i++) { + reset_vec[i] = cpu_to_le32(reset_vec[i]); + } + rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), + memmap[SPIKE_MROM].base, &address_space_memory); + + /* copy in the device tree */ + if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) > + memmap[SPIKE_MROM].size - sizeof(reset_vec)) { + error_report("not enough space to store device-tree"); + exit(1); + } + qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); + rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), + memmap[SPIKE_MROM].base + sizeof(reset_vec), + &address_space_memory); + + /* initialize HTIF using symbols found in load_kernel */ + htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0)); + + /* Core Local Interruptor (timer and IPI) */ + sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, + smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); +} static void spike_v1_10_0_board_init(MachineState *machine) { @@ -172,6 +255,12 @@ static void spike_v1_10_0_board_init(MachineState *machine) MemoryRegion *mask_rom = g_new(MemoryRegion, 1); int i; + if (!qtest_enabled()) { + info_report("The Spike v1.10.0 machine has been deprecated. " + "Please use the generic spike machine and specify the ISA " + "versions using -cpu."); + } + /* Initialize SOC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY, &error_abort, NULL); @@ -254,6 +343,12 @@ static void spike_v1_09_1_board_init(MachineState *machine) MemoryRegion *mask_rom = g_new(MemoryRegion, 1); int i; + if (!qtest_enabled()) { + info_report("The Spike v1.09.1 machine has been deprecated. " + "Please use the generic spike machine and specify the ISA " + "versions using -cpu."); + } + /* Initialize SOC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY, &error_abort, NULL); @@ -359,8 +454,17 @@ static void spike_v1_10_0_machine_init(MachineClass *mc) mc->desc = "RISC-V Spike Board (Privileged ISA v1.10)"; mc->init = spike_v1_10_0_board_init; mc->max_cpus = 1; +} + +static void spike_machine_init(MachineClass *mc) +{ + mc->desc = "RISC-V Spike Board"; + mc->init = spike_board_init; + mc->max_cpus = 1; mc->is_default = 1; + mc->default_cpu_type = SPIKE_V1_10_0_CPU; } DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init) DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init) +DEFINE_MACHINE("spike", spike_machine_init) diff --git a/qemu-deprecated.texi b/qemu-deprecated.texi index 9dca81f461e3..50292d820b0d 100644 --- a/qemu-deprecated.texi +++ b/qemu-deprecated.texi @@ -175,6 +175,12 @@ This machine type uses an unmaintained firmware, broken in lots of ways, and unable to start post-2004 operating systems. 40p machine type should be used instead. +@subsection spike_v1.9.1 and spike_v1.10 (since 4.1) + +The version specific Spike machines have been deprecated in favour of the +generic ``spike`` machine. If you need to specify an older version of the RISC-V +spec you can use the ``-cpu rv64gcsu,priv_spec=v1.9.1`` command line argument. + @section Device options @subsection Block device options -- 2.21.0
WARNING: multiple messages have this Message-ID (diff)
From: Palmer Dabbelt <palmer@sifive.com> To: Peter Maydell <peter.maydell@linaro.org> Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis <Alistair.Francis@wdc.com>, Alistair Francis <alistair.francis@wdc.com>, Igor Mammedov <imammedo@redhat.com>, Palmer Dabbelt <palmer@sifive.com> Subject: [Qemu-riscv] [PULL 18/29] riscv: spike: Add a generic spike machine Date: Sat, 25 May 2019 18:09:37 -0700 [thread overview] Message-ID: <20190526010948.3923-19-palmer@sifive.com> (raw) In-Reply-To: <20190526010948.3923-1-palmer@sifive.com> From: Alistair Francis <Alistair.Francis@wdc.com> Add a generic spike machine (not tied to a version) and deprecate the spike mahines that are tied to a specific version. As we can now specify the CPU via the command line we no londer need specific versions of the spike machines. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> --- hw/riscv/spike.c | 106 ++++++++++++++++++++++++++++++++++++++++++- qemu-deprecated.texi | 6 +++ 2 files changed, 111 insertions(+), 1 deletion(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 2a000a58009a..5b33d4be3bbc 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -39,6 +39,7 @@ #include "chardev/char.h" #include "sysemu/arch_init.h" #include "sysemu/device_tree.h" +#include "sysemu/qtest.h" #include "exec/address-spaces.h" #include "elf.h" @@ -160,7 +161,89 @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap, qemu_fdt_add_subnode(fdt, "/chosen"); qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); } - } +} + +static void spike_board_init(MachineState *machine) +{ + const struct MemmapEntry *memmap = spike_memmap; + + SpikeState *s = g_new0(SpikeState, 1); + MemoryRegion *system_memory = get_system_memory(); + MemoryRegion *main_mem = g_new(MemoryRegion, 1); + MemoryRegion *mask_rom = g_new(MemoryRegion, 1); + int i; + + /* Initialize SOC */ + object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), + TYPE_RISCV_HART_ARRAY, &error_abort, NULL); + object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type", + &error_abort); + object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", + &error_abort); + object_property_set_bool(OBJECT(&s->soc), true, "realized", + &error_abort); + + /* register system main memory (actual RAM) */ + memory_region_init_ram(main_mem, NULL, "riscv.spike.ram", + machine->ram_size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base, + main_mem); + + /* create device tree */ + create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); + + /* boot rom */ + memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom", + memmap[SPIKE_MROM].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, + mask_rom); + + if (machine->kernel_filename) { + load_kernel(machine->kernel_filename); + } + + /* reset vector */ + uint32_t reset_vec[8] = { + 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ + 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ + 0xf1402573, /* csrr a0, mhartid */ +#if defined(TARGET_RISCV32) + 0x0182a283, /* lw t0, 24(t0) */ +#elif defined(TARGET_RISCV64) + 0x0182b283, /* ld t0, 24(t0) */ +#endif + 0x00028067, /* jr t0 */ + 0x00000000, + memmap[SPIKE_DRAM].base, /* start: .dword DRAM_BASE */ + 0x00000000, + /* dtb: */ + }; + + /* copy in the reset vector in little_endian byte order */ + for (i = 0; i < sizeof(reset_vec) >> 2; i++) { + reset_vec[i] = cpu_to_le32(reset_vec[i]); + } + rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), + memmap[SPIKE_MROM].base, &address_space_memory); + + /* copy in the device tree */ + if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) > + memmap[SPIKE_MROM].size - sizeof(reset_vec)) { + error_report("not enough space to store device-tree"); + exit(1); + } + qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); + rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), + memmap[SPIKE_MROM].base + sizeof(reset_vec), + &address_space_memory); + + /* initialize HTIF using symbols found in load_kernel */ + htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0)); + + /* Core Local Interruptor (timer and IPI) */ + sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, + smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); +} static void spike_v1_10_0_board_init(MachineState *machine) { @@ -172,6 +255,12 @@ static void spike_v1_10_0_board_init(MachineState *machine) MemoryRegion *mask_rom = g_new(MemoryRegion, 1); int i; + if (!qtest_enabled()) { + info_report("The Spike v1.10.0 machine has been deprecated. " + "Please use the generic spike machine and specify the ISA " + "versions using -cpu."); + } + /* Initialize SOC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY, &error_abort, NULL); @@ -254,6 +343,12 @@ static void spike_v1_09_1_board_init(MachineState *machine) MemoryRegion *mask_rom = g_new(MemoryRegion, 1); int i; + if (!qtest_enabled()) { + info_report("The Spike v1.09.1 machine has been deprecated. " + "Please use the generic spike machine and specify the ISA " + "versions using -cpu."); + } + /* Initialize SOC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY, &error_abort, NULL); @@ -359,8 +454,17 @@ static void spike_v1_10_0_machine_init(MachineClass *mc) mc->desc = "RISC-V Spike Board (Privileged ISA v1.10)"; mc->init = spike_v1_10_0_board_init; mc->max_cpus = 1; +} + +static void spike_machine_init(MachineClass *mc) +{ + mc->desc = "RISC-V Spike Board"; + mc->init = spike_board_init; + mc->max_cpus = 1; mc->is_default = 1; + mc->default_cpu_type = SPIKE_V1_10_0_CPU; } DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init) DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init) +DEFINE_MACHINE("spike", spike_machine_init) diff --git a/qemu-deprecated.texi b/qemu-deprecated.texi index 9dca81f461e3..50292d820b0d 100644 --- a/qemu-deprecated.texi +++ b/qemu-deprecated.texi @@ -175,6 +175,12 @@ This machine type uses an unmaintained firmware, broken in lots of ways, and unable to start post-2004 operating systems. 40p machine type should be used instead. +@subsection spike_v1.9.1 and spike_v1.10 (since 4.1) + +The version specific Spike machines have been deprecated in favour of the +generic ``spike`` machine. If you need to specify an older version of the RISC-V +spec you can use the ``-cpu rv64gcsu,priv_spec=v1.9.1`` command line argument. + @section Device options @subsection Block device options -- 2.21.0
next prev parent reply other threads:[~2019-05-26 1:30 UTC|newest] Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-05-26 1:09 [Qemu-devel] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 1 Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-devel] [PULL 01/29] SiFive RISC-V GPIO Device Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt 2019-05-30 10:57 ` [Qemu-devel] " Peter Maydell 2019-05-30 10:57 ` [Qemu-riscv] " Peter Maydell 2019-06-14 12:10 ` [Qemu-devel] " Palmer Dabbelt 2019-06-14 12:10 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-17 8:46 ` [Qemu-devel] " Fabien Chouteau 2019-06-17 8:46 ` [Qemu-riscv] " Fabien Chouteau 2019-05-26 1:09 ` [Qemu-devel] [PULL 02/29] target/riscv: Do not allow sfence.vma from user mode Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-devel] [PULL 03/29] RISC-V: fix single stepping over ret and other branching instructions Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-devel] [PULL 04/29] target/riscv: Name the argument sets for all of insn32 formats Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-devel] [PULL 05/29] target/riscv: Use --static-decode for decodetree Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-devel] [PULL 06/29] target/riscv: Merge argument sets for insn32 and insn16 Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-devel] [PULL 07/29] target/riscv: Merge argument decode for RVC shifti Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-devel] [PULL 08/29] target/riscv: Use pattern groups in insn16.decode Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-devel] [PULL 09/29] target/riscv: Split RVC32 and RVC64 insns into separate files Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-devel] [PULL 10/29] target/riscv: Split gen_arith_imm into functional and temp Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-devel] [PULL 11/29] target/riscv: Remove spaces from register names Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-devel] [PULL 12/29] target/riscv: Remove unused include of riscv_htif.h for virt board riscv Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-devel] [PULL 13/29] linux-user/riscv: Add the CPU type as a comment Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-devel] [PULL 14/29] riscv: virt: Allow specifying a CPU via commandline Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-devel] [PULL 15/29] target/riscv: Create settable CPU properties Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-devel] [PULL 16/29] target/riscv: Add a base 32 and 64 bit CPU Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-devel] [PULL 17/29] target/riscv: Deprecate the generic no MMU CPUs Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt 2019-05-26 1:09 ` Palmer Dabbelt [this message] 2019-05-26 1:09 ` [Qemu-riscv] [PULL 18/29] riscv: spike: Add a generic spike machine Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-devel] [PULL 19/29] target/riscv: Mark privilege level 2 as reserved Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-devel] [PULL 20/29] target/riscv: Trigger interrupt on MIP update asynchronously Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-devel] [PULL 21/29] target/riscv: Improve the scause logic Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-devel] [PULL 22/29] target/riscv: Add the MPV and MTL mstatus bits Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-devel] [PULL 23/29] target/riscv: Allow setting mstatus virtulisation bits Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-devel] [PULL 24/29] target/riscv: Add Hypervisor CSR macros Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-devel] [PULL 25/29] target/riscv: Add the HSTATUS register masks Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-devel] [PULL 26/29] target/riscv: Add the HGATP " Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-devel] [PULL 27/29] target/riscv: Add checks for several RVC reserved operands Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-devel] [PULL 28/29] target/riscv: More accurate handling of `sip` CSR Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-devel] [PULL 29/29] target/riscv: Only flush TLB if SATP.ASID changes Palmer Dabbelt 2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt 2019-05-28 11:25 ` [Qemu-devel] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 1 Peter Maydell 2019-05-28 11:25 ` [Qemu-riscv] " Peter Maydell
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