From: Palmer Dabbelt <palmer@sifive.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Jonathan Behrens <jonathan@fintelia.io>,
Alistair Francis <alistair.francis@wdc.com>,
Palmer Dabbelt <palmer@sifive.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 29/29] target/riscv: Only flush TLB if SATP.ASID changes
Date: Sat, 25 May 2019 18:09:48 -0700 [thread overview]
Message-ID: <20190526010948.3923-30-palmer@sifive.com> (raw)
In-Reply-To: <20190526010948.3923-1-palmer@sifive.com>
From: Jonathan Behrens <jonathan@fintelia.io>
There is an analogous change for ARM here:
https://patchwork.kernel.org/patch/10649857
Signed-off-by: Jonathan Behrens <jonathan@fintelia.io>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
target/riscv/csr.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 0f51c7eae241..f9e2910643f8 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -723,7 +723,9 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
return -1;
} else {
- tlb_flush(CPU(riscv_env_get_cpu(env)));
+ if((val ^ env->satp) & SATP_ASID) {
+ tlb_flush(CPU(riscv_env_get_cpu(env)));
+ }
env->satp = val;
}
}
--
2.21.0
WARNING: multiple messages have this Message-ID (diff)
From: Palmer Dabbelt <palmer@sifive.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
Jonathan Behrens <jonathan@fintelia.io>,
Alistair Francis <alistair.francis@wdc.com>,
Palmer Dabbelt <palmer@sifive.com>
Subject: [Qemu-riscv] [PULL 29/29] target/riscv: Only flush TLB if SATP.ASID changes
Date: Sat, 25 May 2019 18:09:48 -0700 [thread overview]
Message-ID: <20190526010948.3923-30-palmer@sifive.com> (raw)
In-Reply-To: <20190526010948.3923-1-palmer@sifive.com>
From: Jonathan Behrens <jonathan@fintelia.io>
There is an analogous change for ARM here:
https://patchwork.kernel.org/patch/10649857
Signed-off-by: Jonathan Behrens <jonathan@fintelia.io>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
target/riscv/csr.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 0f51c7eae241..f9e2910643f8 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -723,7 +723,9 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
return -1;
} else {
- tlb_flush(CPU(riscv_env_get_cpu(env)));
+ if((val ^ env->satp) & SATP_ASID) {
+ tlb_flush(CPU(riscv_env_get_cpu(env)));
+ }
env->satp = val;
}
}
--
2.21.0
next prev parent reply other threads:[~2019-05-26 1:29 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-26 1:09 [Qemu-devel] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 1 Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 01/29] SiFive RISC-V GPIO Device Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt
2019-05-30 10:57 ` [Qemu-devel] " Peter Maydell
2019-05-30 10:57 ` [Qemu-riscv] " Peter Maydell
2019-06-14 12:10 ` [Qemu-devel] " Palmer Dabbelt
2019-06-14 12:10 ` [Qemu-riscv] " Palmer Dabbelt
2019-06-17 8:46 ` [Qemu-devel] " Fabien Chouteau
2019-06-17 8:46 ` [Qemu-riscv] " Fabien Chouteau
2019-05-26 1:09 ` [Qemu-devel] [PULL 02/29] target/riscv: Do not allow sfence.vma from user mode Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 03/29] RISC-V: fix single stepping over ret and other branching instructions Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 04/29] target/riscv: Name the argument sets for all of insn32 formats Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 05/29] target/riscv: Use --static-decode for decodetree Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 06/29] target/riscv: Merge argument sets for insn32 and insn16 Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 07/29] target/riscv: Merge argument decode for RVC shifti Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 08/29] target/riscv: Use pattern groups in insn16.decode Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 09/29] target/riscv: Split RVC32 and RVC64 insns into separate files Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 10/29] target/riscv: Split gen_arith_imm into functional and temp Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 11/29] target/riscv: Remove spaces from register names Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 12/29] target/riscv: Remove unused include of riscv_htif.h for virt board riscv Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 13/29] linux-user/riscv: Add the CPU type as a comment Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 14/29] riscv: virt: Allow specifying a CPU via commandline Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 15/29] target/riscv: Create settable CPU properties Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 16/29] target/riscv: Add a base 32 and 64 bit CPU Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 17/29] target/riscv: Deprecate the generic no MMU CPUs Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 18/29] riscv: spike: Add a generic spike machine Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 19/29] target/riscv: Mark privilege level 2 as reserved Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 20/29] target/riscv: Trigger interrupt on MIP update asynchronously Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 21/29] target/riscv: Improve the scause logic Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 22/29] target/riscv: Add the MPV and MTL mstatus bits Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 23/29] target/riscv: Allow setting mstatus virtulisation bits Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 24/29] target/riscv: Add Hypervisor CSR macros Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 25/29] target/riscv: Add the HSTATUS register masks Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 26/29] target/riscv: Add the HGATP " Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 27/29] target/riscv: Add checks for several RVC reserved operands Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 28/29] target/riscv: More accurate handling of `sip` CSR Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-riscv] " Palmer Dabbelt
2019-05-26 1:09 ` Palmer Dabbelt [this message]
2019-05-26 1:09 ` [Qemu-riscv] [PULL 29/29] target/riscv: Only flush TLB if SATP.ASID changes Palmer Dabbelt
2019-05-28 11:25 ` [Qemu-devel] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 1 Peter Maydell
2019-05-28 11:25 ` [Qemu-riscv] " Peter Maydell
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