From: Lukasz Luba <l.luba@partner.samsung.com>
To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org
Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org,
cw00.choi@samsung.com, kyungmin.park@samsung.com,
m.szyprowski@samsung.com, s.nawrocki@samsung.com,
myungjoo.ham@samsung.com, keescook@chromium.org,
tony@atomide.com, jroedel@suse.de, treding@nvidia.com,
digetx@gmail.com, willy.mh.wolff.ml@gmail.com,
Lukasz Luba <l.luba@partner.samsung.com>
Subject: [PATCH v8 01/13] clk: samsung: add needed IDs for DMC clocks in Exynos5420
Date: Wed, 5 Jun 2019 18:53:58 +0200 [thread overview]
Message-ID: <20190605165410.14606-2-l.luba@partner.samsung.com> (raw)
In-Reply-To: <20190605165410.14606-1-l.luba@partner.samsung.com>
Define new IDs for clocks used by Dynamic Memory Controller in
Exynos5422 SoC.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
include/dt-bindings/clock/exynos5420.h | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 355f469943f1..02d5ac469a3d 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -60,6 +60,7 @@
#define CLK_MAU_EPLL 159
#define CLK_SCLK_HSIC_12M 160
#define CLK_SCLK_MPHY_IXTAL24 161
+#define CLK_SCLK_BPLL 162
/* gate clocks */
#define CLK_UART0 257
@@ -195,6 +196,16 @@
#define CLK_ACLK432_CAM 518
#define CLK_ACLK_FL1550_CAM 519
#define CLK_ACLK550_CAM 520
+#define CLK_CLKM_PHY0 521
+#define CLK_CLKM_PHY1 522
+#define CLK_ACLK_PPMU_DREX0_0 523
+#define CLK_ACLK_PPMU_DREX0_1 524
+#define CLK_ACLK_PPMU_DREX1_0 525
+#define CLK_ACLK_PPMU_DREX1_1 526
+#define CLK_PCLK_PPMU_DREX0_0 527
+#define CLK_PCLK_PPMU_DREX0_1 528
+#define CLK_PCLK_PPMU_DREX1_0 529
+#define CLK_PCLK_PPMU_DREX1_1 530
/* mux clocks */
#define CLK_MOUT_HDMI 640
@@ -217,6 +228,8 @@
#define CLK_MOUT_EPLL 657
#define CLK_MOUT_MAU_EPLL 658
#define CLK_MOUT_USER_MAU_EPLL 659
+#define CLK_MOUT_SCLK_SPLL 660
+#define CLK_MOUT_MX_MSPLL_CCORE_PHY 661
/* divider clocks */
#define CLK_DOUT_PIXEL 768
@@ -248,8 +261,11 @@
#define CLK_DOUT_CCLK_DREX0 794
#define CLK_DOUT_CLK2X_PHY0 795
#define CLK_DOUT_PCLK_CORE_MEM 796
+#define CLK_FF_DOUT_SPLL2 797
+#define CLK_DOUT_PCLK_DREX0 798
+#define CLK_DOUT_PCLK_DREX1 799
/* must be greater than maximal clock id */
-#define CLK_NR_CLKS 797
+#define CLK_NR_CLKS 800
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */
--
2.17.1
next prev parent reply other threads:[~2019-06-05 16:55 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20190605165426eucas1p20524669a299f740b5502db24977b098f@eucas1p2.samsung.com>
2019-06-05 16:53 ` [PATCH v8 00/13] Exynos5 Dynamic Memory Controller driver Lukasz Luba
[not found] ` <CGME20190605165427eucas1p27610c38c96313dd80ab445472735a242@eucas1p2.samsung.com>
2019-06-05 16:53 ` Lukasz Luba [this message]
2019-06-06 8:22 ` [PATCH v8 01/13] clk: samsung: add needed IDs for DMC clocks in Exynos5420 Krzysztof Kozlowski
[not found] ` <CGME20190605165428eucas1p11849754e0d0aa8f8d445ceb0cd6c2f61@eucas1p1.samsung.com>
2019-06-05 16:53 ` [PATCH v8 02/13] clk: samsung: add new clocks for DMC for Exynos5422 SoC Lukasz Luba
2019-06-06 8:34 ` Krzysztof Kozlowski
2019-06-06 9:12 ` Lukasz Luba
2019-06-06 9:45 ` Lukasz Luba
2019-06-06 9:45 ` Lukasz Luba
[not found] ` <CGME20190605165429eucas1p224e803c851c9fd28e3d8737392a8a5c3@eucas1p2.samsung.com>
2019-06-05 16:54 ` [PATCH v8 03/13] clk: samsung: add BPLL rate table for Exynos 5422 SoC Lukasz Luba
2019-06-06 8:25 ` Krzysztof Kozlowski
[not found] ` <CGME20190605165430eucas1p1d3e42d3abbaefbdda9658cb814909fad@eucas1p1.samsung.com>
2019-06-05 16:54 ` [PATCH v8 04/13] dt-bindings: ddr: rename lpddr2 directory Lukasz Luba
[not found] ` <CGME20190605165431eucas1p12810093a1f81f5609782959d878782a0@eucas1p1.samsung.com>
2019-06-05 16:54 ` [PATCH v8 05/13] dt-bindings: ddr: add LPDDR3 memories Lukasz Luba
[not found] ` <CGME20190605165432eucas1p170415ca2025df5b2cefdaa4ae7fb0f64@eucas1p1.samsung.com>
2019-06-05 16:54 ` [PATCH v8 06/13] drivers: memory: extend of_memory by LPDDR3 support Lukasz Luba
2019-06-06 8:27 ` Krzysztof Kozlowski
[not found] ` <CGME20190605165433eucas1p1214f65106df03ae74bbdc95e3eee71f1@eucas1p1.samsung.com>
2019-06-05 16:54 ` [PATCH v8 07/13] dt-bindings: memory-controllers: add Exynos5422 DMC device description Lukasz Luba
2019-06-06 8:29 ` Krzysztof Kozlowski
2019-06-06 10:15 ` Lukasz Luba
[not found] ` <CGME20190605165435eucas1p2fa32f4583f396fdce443b6943ac180d3@eucas1p2.samsung.com>
2019-06-05 16:54 ` [PATCH v8 08/13] drivers: memory: add DMC driver for Exynos5422 Lukasz Luba
2019-06-06 10:03 ` Krzysztof Kozlowski
2019-06-06 10:38 ` Lukasz Luba
2019-06-06 11:45 ` Krzysztof Kozlowski
2019-06-06 13:35 ` Lukasz Luba
[not found] ` <CGME20190605165436eucas1p2219af7e72feef428639ea70f496e3a9c@eucas1p2.samsung.com>
2019-06-05 16:54 ` [PATCH v8 09/13] drivers: devfreq: events: add Exynos PPMU new events Lukasz Luba
[not found] ` <CGME20190605165437eucas1p1321cd8369e1ffc6b4b6c3ca2d69bcd70@eucas1p1.samsung.com>
2019-06-05 16:54 ` [PATCH v8 10/13] ARM: dts: exynos: add chipid label and syscon compatible Lukasz Luba
[not found] ` <CGME20190605165439eucas1p12d9b7aa025fd826d4f880fd7862add62@eucas1p1.samsung.com>
2019-06-05 16:54 ` [PATCH v8 11/13] ARM: dts: exynos: add syscon to clock compatible Lukasz Luba
[not found] ` <CGME20190605165440eucas1p104d84f6485afae10ce9d68cd25200ae1@eucas1p1.samsung.com>
2019-06-05 16:54 ` [PATCH v8 12/13] ARM: dts: exynos: add DMC device for exynos5422 Lukasz Luba
[not found] ` <CGME20190605165441eucas1p1cf771211156e8aca384ed11c6498c263@eucas1p1.samsung.com>
2019-06-05 16:54 ` [PATCH v8 13/13] ARM: exynos_defconfig: enable DMC driver Lukasz Luba
2019-06-06 13:57 ` [PATCH v8 00/13] Exynos5 Dynamic Memory Controller driver Sylwester Nawrocki
2019-06-06 15:03 ` Lukasz Luba
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