From: Julien Grall <julien.grall@arm.com>
To: xen-devel@lists.xenproject.org
Cc: Oleksandr_Tyshchenko@epam.com,
Julien Grall <julien.grall@arm.com>,
Stefano Stabellini <sstabellini@kernel.org>,
Andrii_Anisov@epam.com, Andrii Anisov <andrii.anisov@epam.com>
Subject: [Xen-devel] [PATCH MM-PART3 v3 1/9] xen/arm: Rework HSCTLR_BASE
Date: Fri, 14 Jun 2019 18:51:36 +0100 [thread overview]
Message-ID: <20190614175144.20046-2-julien.grall@arm.com> (raw)
In-Reply-To: <20190614175144.20046-1-julien.grall@arm.com>
The current value of HSCTLR_BASE for Arm64 is pretty wrong. It would
actually turn on SCTLR_EL2.nAA (bit 6) on hardware implementing
ARMv8.4-LSE.
Furthermore, the documentation of what is cleared/set in SCTLR_EL2 is
also not correct and looks like to be a verbatim copy from Arm32.
HSCTLR_BASE is replaced with a bunch of per-architecture new defines
helping to understand better what is the initial value for
SCTLR_EL2/HSCTLR.
Note the defines *_CLEAR are only used to check the state of each bits
are known.
Lastly, the documentation is dropped from arm{32,64}/head.S as it would
be pretty easy to get out-of-sync with the definitions.
Signed-off-by: Julien Grall <julien.grall@arm.com>
Reviewed-by: Andrii Anisov <andrii.anisov@epam.com>
---
Note this patch was part of MM-PART2 before. As this was the only
patch of the series not merged, it is now part of MM-PART3.
Changes in v3:
- Add comment on top of HSCTLR_CLEAR/SCTLR_CLEAR to explain that
it is only used one time at pre-processing time
- Fix typo in the commit message
- Add Andrii's reviewed-by
Changes in v2:
- Use BIT(..., UL) instead of _BITUL
---
xen/arch/arm/arm32/head.S | 12 +--------
xen/arch/arm/arm64/head.S | 10 +-------
xen/include/asm-arm/processor.h | 56 ++++++++++++++++++++++++++++++++++++++++-
3 files changed, 57 insertions(+), 21 deletions(-)
diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S
index 5f817d473e..18ded49a04 100644
--- a/xen/arch/arm/arm32/head.S
+++ b/xen/arch/arm/arm32/head.S
@@ -224,17 +224,7 @@ cpu_init_done:
ldr r0, =(TCR_RES1|TCR_SH0_IS|TCR_ORGN0_WBWA|TCR_IRGN0_WBWA|TCR_T0SZ(0))
mcr CP32(r0, HTCR)
- /*
- * Set up the HSCTLR:
- * Exceptions in LE ARM,
- * Low-latency IRQs disabled,
- * Write-implies-XN disabled (for now),
- * D-cache disabled (for now),
- * I-cache enabled,
- * Alignment checking enabled,
- * MMU translation disabled (for now).
- */
- ldr r0, =(HSCTLR_BASE|SCTLR_Axx_ELx_A)
+ ldr r0, =HSCTLR_SET
mcr CP32(r0, HSCTLR)
/*
diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S
index ddd3a33108..08094a273e 100644
--- a/xen/arch/arm/arm64/head.S
+++ b/xen/arch/arm/arm64/head.S
@@ -352,15 +352,7 @@ skip_bss:
msr tcr_el2, x0
- /* Set up the SCTLR_EL2:
- * Exceptions in LE ARM,
- * Low-latency IRQs disabled,
- * Write-implies-XN disabled (for now),
- * D-cache disabled (for now),
- * I-cache enabled,
- * Alignment checking disabled,
- * MMU translation disabled (for now). */
- ldr x0, =(HSCTLR_BASE)
+ ldr x0, =SCTLR_EL2_SET
msr SCTLR_EL2, x0
/* Ensure that any exceptions encountered at EL2
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index bbcba061ca..e9d2ae2715 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -127,6 +127,9 @@
#define SCTLR_A32_ELx_TE BIT(30, UL)
#define SCTLR_A32_ELx_FI BIT(21, UL)
+/* Common bits for SCTLR_ELx for Arm64 */
+#define SCTLR_A64_ELx_SA BIT(3, UL)
+
/* Common bits for SCTLR_ELx on all architectures */
#define SCTLR_Axx_ELx_EE BIT(25, UL)
#define SCTLR_Axx_ELx_WXN BIT(19, UL)
@@ -135,7 +138,58 @@
#define SCTLR_Axx_ELx_A BIT(1, UL)
#define SCTLR_Axx_ELx_M BIT(0, UL)
-#define HSCTLR_BASE _AC(0x30c51878,U)
+#ifdef CONFIG_ARM_32
+
+#define HSCTLR_RES1 (BIT( 3, UL) | BIT( 4, UL) | BIT( 5, UL) |\
+ BIT( 6, UL) | BIT(11, UL) | BIT(16, UL) |\
+ BIT(18, UL) | BIT(22, UL) | BIT(23, UL) |\
+ BIT(28, UL) | BIT(29, UL))
+
+#define HSCTLR_RES0 (BIT(7, UL) | BIT(8, UL) | BIT(9, UL) | BIT(10, UL) |\
+ BIT(13, UL) | BIT(14, UL) | BIT(15, UL) | BIT(17, UL) |\
+ BIT(20, UL) | BIT(24, UL) | BIT(26, UL) | BIT(27, UL) |\
+ BIT(31, UL))
+
+/* Initial value for HSCTLR */
+#define HSCTLR_SET (HSCTLR_RES1 | SCTLR_Axx_ELx_A | SCTLR_Axx_ELx_I)
+
+/* Only used a pre-processing time... */
+#define HSCTLR_CLEAR (HSCTLR_RES0 | SCTLR_Axx_ELx_M |\
+ SCTLR_Axx_ELx_C | SCTLR_Axx_ELx_WXN |\
+ SCTLR_A32_ELx_FI | SCTLR_Axx_ELx_EE |\
+ SCTLR_A32_ELx_TE)
+
+#if (HSCTLR_SET ^ HSCTLR_CLEAR) != 0xffffffffU
+#error "Inconsistent HSCTLR set/clear bits"
+#endif
+
+#else
+
+#define SCTLR_EL2_RES1 (BIT( 4, UL) | BIT( 5, UL) | BIT(11, UL) |\
+ BIT(16, UL) | BIT(18, UL) | BIT(22, UL) |\
+ BIT(23, UL) | BIT(28, UL) | BIT(29, UL))
+
+#define SCTLR_EL2_RES0 (BIT( 6, UL) | BIT( 7, UL) | BIT( 8, UL) |\
+ BIT( 9, UL) | BIT(10, UL) | BIT(13, UL) |\
+ BIT(14, UL) | BIT(15, UL) | BIT(17, UL) |\
+ BIT(20, UL) | BIT(21, UL) | BIT(24, UL) |\
+ BIT(26, UL) | BIT(27, UL) | BIT(30, UL) |\
+ BIT(31, UL) | (0xffffffffULL << 32))
+
+/* Initial value for SCTLR_EL2 */
+#define SCTLR_EL2_SET (SCTLR_EL2_RES1 | SCTLR_A64_ELx_SA |\
+ SCTLR_Axx_ELx_I)
+
+/* Only used a pre-processing time... */
+#define SCTLR_EL2_CLEAR (SCTLR_EL2_RES0 | SCTLR_Axx_ELx_M |\
+ SCTLR_Axx_ELx_A | SCTLR_Axx_ELx_C |\
+ SCTLR_Axx_ELx_WXN | SCTLR_Axx_ELx_EE)
+
+#if (SCTLR_EL2_SET ^ SCTLR_EL2_CLEAR) != 0xffffffffffffffffUL
+#error "Inconsistent SCTLR_EL2 set/clear bits"
+#endif
+
+#endif
/* HCR Hyp Configuration Register */
#define HCR_RW (_AC(1,UL)<<31) /* Register Width, ARM64 only */
--
2.11.0
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next prev parent reply other threads:[~2019-06-14 17:52 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-14 17:51 [Xen-devel] [PATCH MM-PART3 v3 0/9] xen/arm: Provide a generic function to update Xen PT Julien Grall
2019-06-14 17:51 ` Julien Grall [this message]
2019-06-14 21:05 ` [Xen-devel] [PATCH MM-PART3 v3 1/9] xen/arm: Rework HSCTLR_BASE Stefano Stabellini
2019-06-14 17:51 ` [Xen-devel] [PATCH MM-PART3 v3 2/9] xen/arm: mm: Introduce _PAGE_PRESENT and _PAGE_POPULATE Julien Grall
2019-06-14 21:03 ` Stefano Stabellini
2019-06-14 17:51 ` [Xen-devel] [PATCH MM-PART3 v3 3/9] xen/arm: mm: Sanity check any update of Xen page tables Julien Grall
2019-06-14 21:02 ` Stefano Stabellini
2019-06-14 17:51 ` [Xen-devel] [PATCH MM-PART3 v3 4/9] xen/arm: mm: Rework xen_pt_update_entry to avoid use xenmap_operation Julien Grall
2019-06-14 17:51 ` [Xen-devel] [PATCH MM-PART3 v3 5/9] xen/arm: mm: Remove enum xenmap_operation Julien Grall
2019-06-14 17:51 ` [Xen-devel] [PATCH MM-PART3 v3 6/9] xen/arm: mm: Use {, un}map_domain_page() to map/unmap Xen page-tables Julien Grall
2019-06-14 21:00 ` Stefano Stabellini
2019-06-16 20:23 ` Julien Grall
2019-06-14 17:51 ` [Xen-devel] [PATCH MM-PART3 v3 7/9] xen/arm: mm: Rework Xen page-tables walk during update Julien Grall
2019-06-14 17:51 ` [Xen-devel] [PATCH MM-PART3 v3 8/9] xen/arm: mm: Don't open-code Xen PT update in {set, clear}_fixmap() Julien Grall
2019-06-14 17:51 ` [Xen-devel] [PATCH MM-PART3 v3 9/9] xen/arm: mm: Remove set_pte_flags_on_range() Julien Grall
2019-06-14 20:59 ` Stefano Stabellini
2019-06-16 20:45 ` [Xen-devel] [PATCH MM-PART3 v3 0/9] xen/arm: Provide a generic function to update Xen PT Julien Grall
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