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From: Yoshinori Sato <ysato@users.sourceforge.jp>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org,
	Richard Henderson <richard.henderson@linaro.org>,
	Yoshinori Sato <ysato@users.sourceforge.jp>,
	philmd@redhat.com
Subject: [Qemu-devel] [PATCH v20 11/24] target/rx: Collect all bytes during disassembly
Date: Sun, 16 Jun 2019 23:28:23 +0900	[thread overview]
Message-ID: <20190616142836.10614-12-ysato@users.sourceforge.jp> (raw)
In-Reply-To: <20190616142836.10614-1-ysato@users.sourceforge.jp>

From: Richard Henderson <richard.henderson@linaro.org>

Collected, to be used in the next patch.

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Message-Id: <20190607091116.49044-23-ysato@users.sourceforge.jp>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/rx/disas.c | 62 +++++++++++++++++++++++++++++++++++++------------------
 1 file changed, 42 insertions(+), 20 deletions(-)

diff --git a/target/rx/disas.c b/target/rx/disas.c
index ebc1a44249..5a32a87534 100644
--- a/target/rx/disas.c
+++ b/target/rx/disas.c
@@ -25,43 +25,59 @@ typedef struct DisasContext {
     disassemble_info *dis;
     uint32_t addr;
     uint32_t pc;
+    uint8_t len;
+    uint8_t bytes[8];
 } DisasContext;
 
 
 static uint32_t decode_load_bytes(DisasContext *ctx, uint32_t insn,
-                           int i, int n)
+                                  int i, int n)
 {
-    bfd_byte buf;
+    uint32_t addr = ctx->addr;
+
+    g_assert(ctx->len == i);
+    g_assert(n <= ARRAY_SIZE(ctx->bytes));
+
     while (++i <= n) {
-        ctx->dis->read_memory_func(ctx->addr++, &buf, 1, ctx->dis);
-        insn |= buf << (32 - i * 8);
+        ctx->dis->read_memory_func(addr++, &ctx->bytes[i - 1], 1, ctx->dis);
+        insn |= ctx->bytes[i - 1] << (32 - i * 8);
     }
+    ctx->addr = addr;
+    ctx->len = n;
+
     return insn;
 }
 
 static int32_t li(DisasContext *ctx, int sz)
 {
-    int32_t addr;
-    bfd_byte buf[4];
-    addr = ctx->addr;
+    uint32_t addr = ctx->addr;
+    uintptr_t len = ctx->len;
 
     switch (sz) {
     case 1:
+        g_assert(len + 1 <= ARRAY_SIZE(ctx->bytes));
         ctx->addr += 1;
-        ctx->dis->read_memory_func(addr, buf, 1, ctx->dis);
-        return (int8_t)buf[0];
+        ctx->len += 1;
+        ctx->dis->read_memory_func(addr, ctx->bytes + len, 1, ctx->dis);
+        return (int8_t)ctx->bytes[len];
     case 2:
+        g_assert(len + 2 <= ARRAY_SIZE(ctx->bytes));
         ctx->addr += 2;
-        ctx->dis->read_memory_func(addr, buf, 2, ctx->dis);
-        return ldsw_le_p(buf);
+        ctx->len += 2;
+        ctx->dis->read_memory_func(addr, ctx->bytes + len, 2, ctx->dis);
+        return ldsw_le_p(ctx->bytes + len);
     case 3:
+        g_assert(len + 3 <= ARRAY_SIZE(ctx->bytes));
         ctx->addr += 3;
-        ctx->dis->read_memory_func(addr, buf, 3, ctx->dis);
-        return (int8_t)buf[2] << 16 | lduw_le_p(buf);
+        ctx->len += 3;
+        ctx->dis->read_memory_func(addr, ctx->bytes + len, 3, ctx->dis);
+        return (int8_t)ctx->bytes[len + 2] << 16 | lduw_le_p(ctx->bytes + len);
     case 0:
+        g_assert(len + 4 <= ARRAY_SIZE(ctx->bytes));
         ctx->addr += 4;
-        ctx->dis->read_memory_func(addr, buf, 4, ctx->dis);
-        return ldl_le_p(buf);
+        ctx->len += 4;
+        ctx->dis->read_memory_func(addr, ctx->bytes + len, 4, ctx->dis);
+        return ldl_le_p(ctx->bytes + len);
     default:
         g_assert_not_reached();
     }
@@ -110,7 +126,7 @@ static const char psw[] = {
 static void rx_index_addr(DisasContext *ctx, char out[8], int ld, int mi)
 {
     uint32_t addr = ctx->addr;
-    uint8_t buf[2];
+    uintptr_t len = ctx->len;
     uint16_t dsp;
 
     switch (ld) {
@@ -119,14 +135,18 @@ static void rx_index_addr(DisasContext *ctx, char out[8], int ld, int mi)
         out[0] = '\0';
         return;
     case 1:
+        g_assert(len + 1 <= ARRAY_SIZE(ctx->bytes));
         ctx->addr += 1;
-        ctx->dis->read_memory_func(addr, buf, 1, ctx->dis);
-        dsp = buf[0];
+        ctx->len += 1;
+        ctx->dis->read_memory_func(addr, ctx->bytes + len, 1, ctx->dis);
+        dsp = ctx->bytes[len];
         break;
     case 2:
+        g_assert(len + 2 <= ARRAY_SIZE(ctx->bytes));
         ctx->addr += 2;
-        ctx->dis->read_memory_func(addr, buf, 2, ctx->dis);
-        dsp = lduw_le_p(buf);
+        ctx->len += 2;
+        ctx->dis->read_memory_func(addr, ctx->bytes + len, 2, ctx->dis);
+        dsp = lduw_le_p(ctx->bytes + len);
         break;
     default:
         g_assert_not_reached();
@@ -1392,8 +1412,10 @@ int print_insn_rx(bfd_vma addr, disassemble_info *dis)
     DisasContext ctx;
     uint32_t insn;
     int i;
+
     ctx.dis = dis;
     ctx.pc = ctx.addr = addr;
+    ctx.len = 0;
 
     insn = decode_load(&ctx);
     if (!decode(&ctx, insn)) {
-- 
2.11.0



  parent reply	other threads:[~2019-06-16 15:00 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-16 14:28 [Qemu-devel] [PATCH v20 00/24] Add RX archtecture support Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 01/24] target/rx: TCG translation Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 02/24] target/rx: TCG helper Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 03/24] target/rx: CPU definition Yoshinori Sato
2019-06-16 18:13   ` Igor Mammedov
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 04/24] target/rx: Follow the change of tcg Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 05/24] target/rx: simplify rx_cpu_class_by_name Yoshinori Sato
2019-06-16 18:33   ` Igor Mammedov
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 06/24] target/rx: RX disassembler Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 07/24] target/rx: Disassemble rx_index_addr into a string Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 08/24] target/rx: Replace operand with prt_ldmi in disassembler Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 09/24] target/rx: Use prt_ldmi for XCHG_mr disassembly Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 10/24] target/rx: Emit all disassembly in one prt() Yoshinori Sato
2019-06-16 14:28 ` Yoshinori Sato [this message]
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 12/24] target/rx: Dump bytes for each insn during disassembly Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 13/24] hw/intc: RX62N interrupt controller (ICUa) Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 14/24] hw/timer: RX62N internal timer modules Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 15/24] hw/char: RX62N serial communication interface (SCI) Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 16/24] hw/rx: RX Target hardware definition Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 17/24] target/rx: Move rx_load_image to rx-virt Yoshinori Sato
2019-06-16 18:49   ` Igor Mammedov
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 18/24] hw/rx: Honor -accel qtest Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 19/24] hw/rx: Restrict the RX62N microcontroller to the RX62N CPU core Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 20/24] qemu/bitops.h: Add extract8 and extract16 Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 21/24] hw/registerfields.h: Add 8bit and 16bit register macros Yoshinori Sato
2019-06-16 19:06   ` Igor Mammedov
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 22/24] Add rx-softmmu Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 23/24] MAINTAINERS: Add RX Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 24/24] BootLinuxConsoleTest: Test the RX-Virt machine Yoshinori Sato
2019-06-16 15:18 ` [Qemu-devel] [PATCH v20 00/24] Add RX archtecture support no-reply
2019-06-16 19:08   ` Igor Mammedov
2019-06-16 15:55 ` no-reply
2019-06-16 16:45 ` no-reply
2019-06-16 17:26 ` no-reply
2019-06-16 17:33 ` no-reply
2019-06-16 18:00 ` no-reply
2019-06-16 18:18 ` no-reply

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