From: "René van Dorst" <opensource@vdorst.com> To: Sean Wang <sean.wang@mediatek.com>, Florian Fainelli <f.fainelli@gmail.com>, "David S . Miller" <davem@davemloft.net>, Matthias Brugger <matthias.bgg@gmail.com>, Andrew Lunn <andrew@lunn.ch>, Vivien Didelot <vivien.didelot@gmail.com> Cc: netdev@vger.kernel.org, john@phrozen.org, linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, "René van Dorst" <opensource@vdorst.com> Subject: [PATCH net-next 1/2] net: ethernet: mediatek: Add MT7621 TRGMII mode support Date: Sun, 16 Jun 2019 20:20:09 +0200 [thread overview] Message-ID: <20190616182010.18778-2-opensource@vdorst.com> (raw) In-Reply-To: <20190616182010.18778-1-opensource@vdorst.com> MT7621 SOC also supports TRGMII. TRGMII speed is 1200MBit. Signed-off-by: René van Dorst <opensource@vdorst.com> --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 38 ++++++++++++++++++--- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 11 ++++++ 2 files changed, 45 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index 362eacd82b92..628adbf79710 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -140,6 +140,28 @@ static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) return _mtk_mdio_read(eth, phy_addr, phy_reg); } +static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth, + phy_interface_t interface) +{ + u32 val; + + /* Check DDR memory type. Currently DDR2 is not supported. */ + regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val); + if (val & SYSCFG_DRAM_TYPE_DDR2) { + dev_err(eth->dev, + "TRGMII mode with DDR2 memory is not supported!\n"); + return -EOPNOTSUPP; + } + + val = (interface == PHY_INTERFACE_MODE_TRGMII) ? + ETHSYS_TRGMII_MT7621_DDR_PLL : 0; + + regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, + ETHSYS_TRGMII_MT7621_MASK, val); + + return 0; +} + static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed) { u32 val; @@ -189,9 +211,17 @@ static void mtk_phy_link_adjust(struct net_device *dev) break; } - if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) && - !mac->id && !mac->trgmii) - mtk_gmac0_rgmii_adjust(mac->hw, dev->phydev->speed); + if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) && !mac->id) { + if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII_MT7621_CLK)) { + if (mt7621_gmac0_rgmii_adjust(mac->hw, + dev->phydev->interface)) + return; + } else { + if (!mac->trgmii) + mtk_gmac0_rgmii_adjust(mac->hw, + dev->phydev->speed); + } + } if (dev->phydev->link) mcr |= MAC_MCR_FORCE_LINK; @@ -2613,7 +2643,7 @@ static const struct mtk_soc_data mt2701_data = { }; static const struct mtk_soc_data mt7621_data = { - .caps = MTK_SHARED_INT, + .caps = MT7621_CAPS, .required_clks = MT7621_CLKS_BITMAP, .required_pctl = false, }; diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h index a0aa5008d5cc..9abb4015477f 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -369,6 +369,10 @@ #define MT7622_ETH 7622 #define MT7621_ETH 7621 +/* ethernet system control register */ +#define ETHSYS_SYSCFG 0x10 +#define SYSCFG_DRAM_TYPE_DDR2 BIT(4) + /* ethernet subsystem config register */ #define ETHSYS_SYSCFG0 0x14 #define SYSCFG0_GE_MASK 0x3 @@ -383,6 +387,9 @@ /* ethernet subsystem clock register */ #define ETHSYS_CLKCFG0 0x2c #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) +#define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6)) +#define ETHSYS_TRGMII_MT7621_APLL BIT(6) +#define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5) /* ethernet reset control register */ #define ETHSYS_RSTCTRL 0x34 @@ -622,6 +629,7 @@ enum mtk_eth_path { #define MTK_SHARED_SGMII BIT(7) #define MTK_HWLRO BIT(8) #define MTK_SHARED_INT BIT(9) +#define MTK_TRGMII_MT7621_CLK BIT(10) /* Supported path present on SoCs */ #define MTK_PATH_BIT(x) BIT((x) + 10) @@ -673,6 +681,9 @@ enum mtk_eth_path { #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) +#define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ + MTK_GMAC2_RGMII | MTK_SHARED_INT | MTK_TRGMII_MT7621_CLK) + #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ MTK_MUX_GDM1_TO_GMAC1_ESW | \ -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: "René van Dorst" <opensource-91nzXlUTePbQT0dZR+AlfA@public.gmane.org> To: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>, Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>, "David S . Miller" <davem-fT/PcQaiUtIeIZ0/mPfg9Q@public.gmane.org>, Matthias Brugger <matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>, Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>, Vivien Didelot <vivien.didelot-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Cc: "René van Dorst" <opensource-91nzXlUTePbQT0dZR+AlfA@public.gmane.org>, netdev-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-mips-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, john-Pj+rj9U5foFAfugRpC6u6w@public.gmane.org Subject: [PATCH net-next 1/2] net: ethernet: mediatek: Add MT7621 TRGMII mode support Date: Sun, 16 Jun 2019 20:20:09 +0200 [thread overview] Message-ID: <20190616182010.18778-2-opensource@vdorst.com> (raw) In-Reply-To: <20190616182010.18778-1-opensource-91nzXlUTePbQT0dZR+AlfA@public.gmane.org> MT7621 SOC also supports TRGMII. TRGMII speed is 1200MBit. Signed-off-by: René van Dorst <opensource@vdorst.com> --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 38 ++++++++++++++++++--- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 11 ++++++ 2 files changed, 45 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index 362eacd82b92..628adbf79710 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -140,6 +140,28 @@ static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) return _mtk_mdio_read(eth, phy_addr, phy_reg); } +static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth, + phy_interface_t interface) +{ + u32 val; + + /* Check DDR memory type. Currently DDR2 is not supported. */ + regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val); + if (val & SYSCFG_DRAM_TYPE_DDR2) { + dev_err(eth->dev, + "TRGMII mode with DDR2 memory is not supported!\n"); + return -EOPNOTSUPP; + } + + val = (interface == PHY_INTERFACE_MODE_TRGMII) ? + ETHSYS_TRGMII_MT7621_DDR_PLL : 0; + + regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, + ETHSYS_TRGMII_MT7621_MASK, val); + + return 0; +} + static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed) { u32 val; @@ -189,9 +211,17 @@ static void mtk_phy_link_adjust(struct net_device *dev) break; } - if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) && - !mac->id && !mac->trgmii) - mtk_gmac0_rgmii_adjust(mac->hw, dev->phydev->speed); + if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) && !mac->id) { + if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII_MT7621_CLK)) { + if (mt7621_gmac0_rgmii_adjust(mac->hw, + dev->phydev->interface)) + return; + } else { + if (!mac->trgmii) + mtk_gmac0_rgmii_adjust(mac->hw, + dev->phydev->speed); + } + } if (dev->phydev->link) mcr |= MAC_MCR_FORCE_LINK; @@ -2613,7 +2643,7 @@ static const struct mtk_soc_data mt2701_data = { }; static const struct mtk_soc_data mt7621_data = { - .caps = MTK_SHARED_INT, + .caps = MT7621_CAPS, .required_clks = MT7621_CLKS_BITMAP, .required_pctl = false, }; diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h index a0aa5008d5cc..9abb4015477f 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -369,6 +369,10 @@ #define MT7622_ETH 7622 #define MT7621_ETH 7621 +/* ethernet system control register */ +#define ETHSYS_SYSCFG 0x10 +#define SYSCFG_DRAM_TYPE_DDR2 BIT(4) + /* ethernet subsystem config register */ #define ETHSYS_SYSCFG0 0x14 #define SYSCFG0_GE_MASK 0x3 @@ -383,6 +387,9 @@ /* ethernet subsystem clock register */ #define ETHSYS_CLKCFG0 0x2c #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) +#define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6)) +#define ETHSYS_TRGMII_MT7621_APLL BIT(6) +#define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5) /* ethernet reset control register */ #define ETHSYS_RSTCTRL 0x34 @@ -622,6 +629,7 @@ enum mtk_eth_path { #define MTK_SHARED_SGMII BIT(7) #define MTK_HWLRO BIT(8) #define MTK_SHARED_INT BIT(9) +#define MTK_TRGMII_MT7621_CLK BIT(10) /* Supported path present on SoCs */ #define MTK_PATH_BIT(x) BIT((x) + 10) @@ -673,6 +681,9 @@ enum mtk_eth_path { #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) +#define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ + MTK_GMAC2_RGMII | MTK_SHARED_INT | MTK_TRGMII_MT7621_CLK) + #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ MTK_MUX_GDM1_TO_GMAC1_ESW | \ -- 2.20.1 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek
next prev parent reply other threads:[~2019-06-16 18:30 UTC|newest] Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-06-16 18:20 [PATCH net-next 0/2] net: mediatek: Add MT7621 TRGMII mode support René van Dorst 2019-06-16 18:20 ` René van Dorst 2019-06-16 18:20 ` René van Dorst [this message] 2019-06-16 18:20 ` [PATCH net-next 1/2] net: ethernet: " René van Dorst 2019-06-16 18:20 ` [PATCH net-next 2/2] net: dsa: mt7530: " René van Dorst 2019-06-16 18:20 ` René van Dorst 2019-06-17 14:02 ` [PATCH net-next 0/2] net: mediatek: " Andrew Lunn 2019-06-17 21:33 ` René van Dorst 2019-06-17 21:44 ` Andrew Lunn 2019-06-17 23:20 ` René van Dorst 2019-06-18 1:53 ` Andrew Lunn 2019-06-18 1:53 ` Andrew Lunn 2019-06-18 2:21 ` Florian Fainelli 2019-06-18 11:46 ` René van Dorst 2019-06-17 22:19 ` Florian Fainelli
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