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From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Gregory Clement <gregory.clement@bootlin.com>,
	Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,
	Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
	Kishon Vijay Abraham I <kishon@ti.com>
Cc: devicetree@vger.kernel.org,
	Antoine Tenart <antoine.tenart@bootlin.com>,
	Grzegorz Jaszczyk <jaz@semihalf.com>,
	Russell King <linux@armlinux.org.uk>,
	Maxime Chevallier <maxime.chevallier@bootlin.com>,
	Nadav Haklai <nadavh@marvell.com>,
	Rob Herring <robh+dt@kernel.org>,
	Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	Miquel Raynal <miquel.raynal@bootlin.com>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 14/19] dt-bindings: pci: add PHY properties to Armada 7K/8K controller bindings
Date: Thu, 27 Jun 2019 14:25:00 +0200	[thread overview]
Message-ID: <20190627122505.25774-2-miquel.raynal@bootlin.com> (raw)
In-Reply-To: <20190627122505.25774-1-miquel.raynal@bootlin.com>

Armada CP110 PCIe controller can have a PHY (for configuring SERDES
lanes). Describe these two properties in the bindings.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
 Documentation/devicetree/bindings/pci/pci-armada8k.txt | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt
index 9e3fc15e1af8..a373a80524db 100644
--- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt
+++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt
@@ -17,6 +17,10 @@ Required properties:
    name must be "core" for the first clock and "reg" for the second
    one
 
+Optional properties:
+- phys: phandle to the PHY node (generic PHY bindings).
+- phy-names: names of the PHYs.
+
 Example:
 
 	pcie@f2600000 {
-- 
2.19.1

WARNING: multiple messages have this Message-ID (diff)
From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Gregory Clement <gregory.clement@bootlin.com>,
	Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,
	Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
	Kishon Vijay Abraham I <kishon@ti.com>
Cc: devicetree@vger.kernel.org,
	Antoine Tenart <antoine.tenart@bootlin.com>,
	Grzegorz Jaszczyk <jaz@semihalf.com>,
	Russell King <linux@armlinux.org.uk>,
	Maxime Chevallier <maxime.chevallier@bootlin.com>,
	Nadav Haklai <nadavh@marvell.com>,
	Rob Herring <robh+dt@kernel.org>,
	Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	Miquel Raynal <miquel.raynal@bootlin.com>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 14/19] dt-bindings: pci: add PHY properties to Armada 7K/8K controller bindings
Date: Thu, 27 Jun 2019 14:25:00 +0200	[thread overview]
Message-ID: <20190627122505.25774-2-miquel.raynal@bootlin.com> (raw)
In-Reply-To: <20190627122505.25774-1-miquel.raynal@bootlin.com>

Armada CP110 PCIe controller can have a PHY (for configuring SERDES
lanes). Describe these two properties in the bindings.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
 Documentation/devicetree/bindings/pci/pci-armada8k.txt | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt
index 9e3fc15e1af8..a373a80524db 100644
--- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt
+++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt
@@ -17,6 +17,10 @@ Required properties:
    name must be "core" for the first clock and "reg" for the second
    one
 
+Optional properties:
+- phys: phandle to the PHY node (generic PHY bindings).
+- phy-names: names of the PHYs.
+
 Example:
 
 	pcie@f2600000 {
-- 
2.19.1


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  reply	other threads:[~2019-06-27 12:25 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-27  9:50 [PATCH v2 00/19] Enhance CP110 COMPHY support Miquel Raynal
2019-06-27  9:50 ` [PATCH v2 01/19] phy: mvebu-cp110-comphy: Add clocks support Miquel Raynal
2019-06-27  9:50   ` Miquel Raynal
2019-07-29  8:06   ` Grzegorz Jaszczyk
2019-07-29  8:10   ` Grzegorz Jaszczyk
2019-06-27  9:50 ` [PATCH v2 02/19] phy: mvebu-cp110-comphy: Explicitly initialize the lane submode Miquel Raynal
2019-06-27  9:50   ` Miquel Raynal
2019-06-27  9:50 ` [PATCH v2 03/19] phy: mvebu-cp110-comphy: Add SMC call support Miquel Raynal
2019-06-27  9:50   ` Miquel Raynal
2019-07-23  8:48   ` Maxime Chevallier
2019-07-23  8:48     ` Maxime Chevallier
2019-06-27  9:50 ` [PATCH v2 04/19] phy: mvebu-cp110-comphy: List already supported Ethernet modes Miquel Raynal
2019-06-27  9:50   ` Miquel Raynal
2019-06-27  9:50 ` [PATCH v2 05/19] phy: mvebu-cp110-comphy: Add RXAUI support Miquel Raynal
2019-06-27  9:50   ` Miquel Raynal
2019-06-27  9:50 ` [PATCH v2 06/19] phy: mvebu-cp110-comphy: Rename the macro handling only Ethernet modes Miquel Raynal
2019-06-27  9:50   ` Miquel Raynal
2019-06-27  9:50 ` [PATCH v2 07/19] phy: mvebu-cp110-comphy: Allow non-Ethernet modes to be configured Miquel Raynal
2019-06-27  9:50   ` Miquel Raynal
2019-06-27  9:50 ` [PATCH v2 08/19] phy: mvebu-cp110-comphy: Add USB3 host/device support Miquel Raynal
2019-06-27  9:50   ` Miquel Raynal
2019-06-27  9:50 ` [PATCH v2 09/19] phy: mvebu-cp110-comphy: Add SATA support Miquel Raynal
2019-06-27  9:50   ` Miquel Raynal
2019-06-27  9:50 ` [PATCH v2 10/19] phy: mvebu-cp110-comphy: Cosmetic change in a helper Miquel Raynal
2019-06-27  9:50   ` Miquel Raynal
2019-06-27  9:50 ` [PATCH v2 11/19] phy: mvebu-cp110-comphy: Add PCIe support Miquel Raynal
2019-06-27  9:50   ` Miquel Raynal
2019-06-27  9:50 ` [PATCH v2 12/19] phy: mvebu-cp110-comphy: Update comment about powering off all lanes at boot Miquel Raynal
2019-06-27  9:50   ` Miquel Raynal
2019-06-27 12:24 ` [PATCH v2 13/19] dt-bindings: phy: Add Marvell COMPHY clocks Miquel Raynal
2019-06-27 12:24   ` Miquel Raynal
2019-06-27 12:25   ` Miquel Raynal [this message]
2019-06-27 12:25     ` [PATCH v2 14/19] dt-bindings: pci: add PHY properties to Armada 7K/8K controller bindings Miquel Raynal
2019-07-22 17:52     ` Rob Herring
2019-07-22 17:52       ` Rob Herring
2019-07-23  8:35       ` Miquel Raynal
2019-07-24 15:56       ` Miquel Raynal
2019-06-27 12:25   ` [PATCH v2 15/19] arm64: dts: marvell: Add CP110 COMPHY clocks Miquel Raynal
2019-06-27 12:25     ` Miquel Raynal
2019-06-27 12:25   ` [PATCH v2 16/19] arm64: dts: marvell: Add 7k/8k per-port PHYs in SATA nodes Miquel Raynal
2019-06-27 12:25     ` Miquel Raynal
2019-06-27 12:25   ` [PATCH v2 17/19] arm64: dts: marvell: Add 7k/8k PHYs in USB3 nodes Miquel Raynal
2019-06-27 12:25     ` Miquel Raynal
2019-06-27 12:25   ` [PATCH v2 18/19] arm64: dts: marvell: Add 7k/8k PHYs in PCIe nodes Miquel Raynal
2019-06-27 12:25     ` Miquel Raynal
2019-06-27 12:25   ` [PATCH v2 19/19] arm64: dts: marvell: Convert 7k/8k usb-phy properties to phy-supply Miquel Raynal
2019-06-27 12:25     ` Miquel Raynal
2019-07-22 17:51   ` [PATCH v2 13/19] dt-bindings: phy: Add Marvell COMPHY clocks Rob Herring
2019-07-22 17:51     ` Rob Herring

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