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From: Moritz Fischer <mdf@kernel.org>
To: linux-fpga@vger.kernel.org, gregkh@linuxfoundation.org
Cc: linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org,
	Wu Hao <hao.wu@intel.com>, Xu Yilun <yilun.xu@intel.com>,
	Alan Tull <atull@kernel.org>, Moritz Fischer <mdf@kernel.org>
Subject: [PATCH 03/15] fpga: dfl: fme: align PR buffer size per PR datawidth
Date: Thu, 27 Jun 2019 17:49:39 -0700	[thread overview]
Message-ID: <20190628004951.6202-4-mdf@kernel.org> (raw)
In-Reply-To: <20190628004951.6202-1-mdf@kernel.org>

From: Wu Hao <hao.wu@intel.com>

Current driver checks if input bitstream file size is aligned or
not per PR data width (default 32bits). It requires one additional
step for end user when they generate the bitstream file, padding
extra zeros to bitstream file to align its size per PR data width,
but they don't have to as hardware will drop extra padding bytes
automatically.

In order to simplify the user steps, this patch aligns PR buffer
size per PR data width in driver, to allow user to pass unaligned
size bitstream files to driver.

Signed-off-by: Xu Yilun <yilun.xu@intel.com>
Signed-off-by: Wu Hao <hao.wu@intel.com>
Acked-by: Alan Tull <atull@kernel.org>
Acked-by: Moritz Fischer <mdf@kernel.org>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
---
 drivers/fpga/dfl-fme-pr.c | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/fpga/dfl-fme-pr.c b/drivers/fpga/dfl-fme-pr.c
index 6ec0f09e5994..3c71dc3faaf5 100644
--- a/drivers/fpga/dfl-fme-pr.c
+++ b/drivers/fpga/dfl-fme-pr.c
@@ -74,6 +74,7 @@ static int fme_pr(struct platform_device *pdev, unsigned long arg)
 	struct dfl_fme *fme;
 	unsigned long minsz;
 	void *buf = NULL;
+	size_t length;
 	int ret = 0;
 	u64 v;
 
@@ -85,9 +86,6 @@ static int fme_pr(struct platform_device *pdev, unsigned long arg)
 	if (port_pr.argsz < minsz || port_pr.flags)
 		return -EINVAL;
 
-	if (!IS_ALIGNED(port_pr.buffer_size, 4))
-		return -EINVAL;
-
 	/* get fme header region */
 	fme_hdr = dfl_get_feature_ioaddr_by_id(&pdev->dev,
 					       FME_FEATURE_ID_HEADER);
@@ -103,7 +101,13 @@ static int fme_pr(struct platform_device *pdev, unsigned long arg)
 		       port_pr.buffer_size))
 		return -EFAULT;
 
-	buf = vmalloc(port_pr.buffer_size);
+	/*
+	 * align PR buffer per PR bandwidth, as HW ignores the extra padding
+	 * data automatically.
+	 */
+	length = ALIGN(port_pr.buffer_size, 4);
+
+	buf = vmalloc(length);
 	if (!buf)
 		return -ENOMEM;
 
@@ -140,7 +144,7 @@ static int fme_pr(struct platform_device *pdev, unsigned long arg)
 	fpga_image_info_free(region->info);
 
 	info->buf = buf;
-	info->count = port_pr.buffer_size;
+	info->count = length;
 	info->region_id = port_pr.port_id;
 	region->info = info;
 
-- 
2.22.0


  parent reply	other threads:[~2019-06-28  0:50 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-28  0:49 [PATCH 00/15] FPGA DFL updates Moritz Fischer
2019-06-28  0:49 ` [PATCH 01/15] fpga: dfl-fme-mgr: fix FME_PR_INTFC_ID register address Moritz Fischer
2019-06-28  0:49 ` [PATCH 02/15] fpga: dfl: fme: remove copy_to_user() in ioctl for PR Moritz Fischer
2019-06-28  0:49 ` Moritz Fischer [this message]
2019-06-28  0:49 ` [PATCH 04/15] fpga: dfl: fme: support 512bit data width PR Moritz Fischer
2019-07-03 17:56   ` Greg KH
2019-07-03 23:44     ` Wu Hao
2019-06-28  0:49 ` [PATCH 05/15] Documentation: fpga: dfl: add descriptions for virtualization and new interfaces Moritz Fischer
2019-07-03 17:59   ` Greg KH
2019-07-03 23:38     ` Wu Hao
2019-07-04  5:37       ` Greg KH
2019-07-04  6:42         ` Wu Hao
2019-07-04  8:17           ` Greg KH
2019-07-04  8:19             ` Wu Hao
2019-06-28  0:49 ` [PATCH 06/15] fpga: dfl: fme: add DFL_FPGA_FME_PORT_RELEASE/ASSIGN ioctl support Moritz Fischer
2019-07-03 18:07   ` Greg KH
2019-07-03 23:30     ` Wu Hao
2019-07-04  5:39       ` Greg KH
2019-07-04  6:31         ` Wu Hao
2019-07-04  8:20           ` Greg KH
2019-07-04  8:58             ` Wu Hao
2019-07-04 11:04               ` Greg KH
2019-07-04 11:29                 ` Wu Hao
2019-06-28  0:49 ` [PATCH 07/15] fpga: dfl: pci: enable SRIOV support Moritz Fischer
2019-06-28  0:49 ` [PATCH 08/15] fpga: dfl: afu: add AFU state related sysfs interfaces Moritz Fischer
2019-06-28  0:49 ` [PATCH 09/15] fpga: dfl: afu: add userclock " Moritz Fischer
2019-06-28  0:49 ` [PATCH 10/15] fpga: dfl: add id_table for dfl private feature driver Moritz Fischer
2019-06-28  0:49 ` [PATCH 11/15] fpga: dfl: afu: export __port_enable/disable function Moritz Fischer
2019-06-28  0:49 ` [PATCH 12/15] fpga: dfl: afu: add error reporting support Moritz Fischer
2019-06-28  0:49 ` [PATCH 13/15] fpga: dfl: afu: add STP (SignalTap) support Moritz Fischer
2019-06-28  0:49 ` [PATCH 14/15] fpga: dfl: fme: add capability sysfs interfaces Moritz Fischer
2019-06-28  0:49 ` [PATCH 15/15] fpga: dfl: fme: add global error reporting support Moritz Fischer

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