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From: Jan Bobek <jan.bobek@gmail.com>
To: qemu-devel@nongnu.org
Cc: "Jan Bobek" <jan.bobek@gmail.com>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"Richard Henderson" <richard.henderson@linaro.org>
Subject: [Qemu-devel] [RISU RFC PATCH v2 10/14] x86.risu: add SSSE3 instructions
Date: Mon,  1 Jul 2019 00:35:32 -0400	[thread overview]
Message-ID: <20190701043536.26019-11-jan.bobek@gmail.com> (raw)
In-Reply-To: <20190701043536.26019-1-jan.bobek@gmail.com>

Add SSSE3 instructions to the x86 configuration file.

Signed-off-by: Jan Bobek <jan.bobek@gmail.com>
---
 x86.risu | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/x86.risu b/x86.risu
index 01181dd..35992d6 100644
--- a/x86.risu
+++ b/x86.risu
@@ -77,6 +77,13 @@ ADDPD           SSE2    00001111 01011000 !emit { data16(); modrm(); mem(size =>
 ADDSS           SSE     00001111 01011000 !emit { rep(); modrm(); mem(size => 4); }
 ADDSD           SSE2    00001111 01011000 !emit { repne(); modrm(); mem(size => 8); }
 
+PHADDW_64       SSSE3   00001111 00111000 00000001 !emit { modrm(); mem(size => 8); }
+PHADDW          SSSE3   00001111 00111000 00000001 !emit { data16(); modrm(); mem(size => 16, align => 16); }
+PHADDD_64       SSSE3   00001111 00111000 00000010 !emit { modrm(); mem(size => 8); }
+PHADDD          SSSE3   00001111 00111000 00000010 !emit { data16(); modrm(); mem(size => 16, align => 16); }
+PHADDSW_64      SSSE3   00001111 00111000 00000011 !emit { modrm(); mem(size => 8); }
+PHADDSW         SSSE3   00001111 00111000 00000011 !emit { data16(); modrm(); mem(size => 16, align => 16); }
+
 HADDPS          SSE3    00001111 01111100 !emit { repne(); modrm(); mem(size => 16, align => 16); }
 HADDPD          SSE3    00001111 01111100 !emit { data16(); modrm(); mem(size => 16, align => 16); }
 
@@ -102,6 +109,13 @@ SUBPD           SSE2    00001111 01011100 !emit { data16(); modrm(); mem(size =>
 SUBSS           SSE     00001111 01011100 !emit { rep(); modrm(); mem(size => 4); }
 SUBSD           SSE2    00001111 01011100 !emit { repne(); modrm(); mem(size => 8); }
 
+PHSUBW_64       SSSE3   00001111 00111000 00000101 !emit { modrm(); mem(size => 8); }
+PHSUBW          SSSE3   00001111 00111000 00000101 !emit { data16(); modrm(); mem(size => 16, align => 16); }
+PHSUBD_64       SSSE3   00001111 00111000 00000110 !emit { modrm(); mem(size => 8); }
+PHSUBD          SSSE3   00001111 00111000 00000110 !emit { data16(); modrm(); mem(size => 16, align => 16); }
+PHSUBSW_64      SSSE3   00001111 00111000 00000111 !emit { modrm(); mem(size => 8); }
+PHSUBSW         SSSE3   00001111 00111000 00000111 !emit { data16(); modrm(); mem(size => 16, align => 16); }
+
 HSUBPS          SSE3    00001111 01111101 !emit { repne(); modrm(); mem(size => 16, align => 16); }
 HSUBPD          SSE3    00001111 01111101 !emit { data16(); modrm(); mem(size => 16, align => 16); }
 
@@ -117,6 +131,9 @@ PMULHUW         SSE2    00001111 11100100 !emit { data16(); modrm(); mem(size =>
 PMULUDQ_64      SSE2    00001111 11110100 !emit { modrm(); mem(size => 8); }
 PMULUDQ         SSE2    00001111 11110100 !emit { data16(); modrm(); mem(size => 16, align => 16); }
 
+PMULHRSW_64     SSSE3   00001111 00111000 00001011 !emit { modrm(); mem(size => 8); }
+PMULHRSW        SSSE3   00001111 00111000 00001011 !emit { data16(); modrm(); mem(size => 16, align => 16); }
+
 MULPS           SSE     00001111 01011001 !emit { modrm(); mem(size => 16, align => 16); }
 MULPD           SSE2    00001111 01011001 !emit { data16(); modrm(); mem(size => 16, align => 16); }
 MULSS           SSE     00001111 01011001 !emit { rep(); modrm(); mem(size => 4); }
@@ -124,6 +141,8 @@ MULSD           SSE2    00001111 01011001 !emit { repne(); modrm(); mem(size =>
 
 PMADDWD         MMX     00001111 11110101 !emit { modrm(); mem(size => 8); }
 PMADDWD         SSE2    00001111 11110101 !emit { data16(); modrm(); mem(size => 16, align => 16); }
+PMADDUBSW_64    SSSE3   00001111 00111000 00000100 !emit { modrm(); mem(size => 8); }
+PMADDUBSW       SSSE3   00001111 00111000 00000100 !emit { data16(); modrm(); mem(size => 16, align => 16); }
 
 DIVPS           SSE     00001111 01011110 !emit { modrm(); mem(size => 16, align => 16); }
 DIVPD           SSE2    00001111 01011110 !emit { data16(); modrm(); mem(size => 16, align => 16); }
@@ -169,6 +188,20 @@ PAVGW           SSE2    00001111 11100011 !emit { data16(); modrm(); mem(size =>
 PSADBW          SSE     00001111 11110110 !emit { modrm(); mem(size => 8); }
 PSADBW          SSE2    00001111 11110110 !emit { data16(); modrm(); mem(size => 16, align => 16); }
 
+PABSB_64        SSSE3   00001111 00111000 00011100 !emit { modrm(); mem(size => 8); }
+PABSB           SSSE3   00001111 00111000 00011100 !emit { data16(); modrm(); mem(size => 16, align => 16); }
+PABSW_64        SSSE3   00001111 00111000 00011101 !emit { modrm(); mem(size => 8); }
+PABSW           SSSE3   00001111 00111000 00011101 !emit { data16(); modrm(); mem(size => 16, align => 16); }
+PABSD_64        SSSE3   00001111 00111000 00011110 !emit { modrm(); mem(size => 8); }
+PABSD           SSSE3   00001111 00111000 00011110 !emit { data16(); modrm(); mem(size => 16, align => 16); }
+
+PSIGNB_64       SSSE3   00001111 00111000 00001000 !emit { modrm(); mem(size => 8); }
+PSIGNB          SSSE3   00001111 00111000 00001000 !emit { data16(); modrm(); mem(size => 16, align => 16); }
+PSIGNW_64       SSSE3   00001111 00111000 00001001 !emit { modrm(); mem(size => 8); }
+PSIGNW          SSSE3   00001111 00111000 00001001 !emit { data16(); modrm(); mem(size => 16, align => 16); }
+PSIGND_64       SSSE3   00001111 00111000 00001010 !emit { modrm(); mem(size => 8); }
+PSIGND          SSSE3   00001111 00111000 00001010 !emit { data16(); modrm(); mem(size => 16, align => 16); }
+
 # Comparison Instructions
 PCMPEQB         MMX     00001111 01110100 !emit { modrm(); mem(size => 8); }
 PCMPEQB         SSE2    00001111 01110100 !emit { data16(); modrm(); mem(size => 16, align => 16); }
@@ -256,6 +289,9 @@ PSRAW_imm       SSE2    00001111 01110001 !emit { data16(); modrm(mod => MOD_DIR
 PSRAD_imm       MMX     00001111 01110010 !emit { modrm(mod => MOD_DIRECT, reg => 4); imm(size => 1); }
 PSRAD_imm       SSE2    00001111 01110010 !emit { data16(); modrm(mod => MOD_DIRECT, reg => 4); imm(size => 1); }
 
+PALIGNR_64      SSSE3   00001111 00111010 00001111 !emit { modrm(); mem(size => 8); imm(size => 1); }
+PALIGNR         SSSE3   00001111 00111010 00001111 !emit { data16(); modrm(); mem(size => 16, align => 16); imm(size => 1); }
+
 # Shuffle, Unpack, Blend, Insert, Extract, Broadcast, Permute, Scatter Instructions
 PACKSSWB        MMX     00001111 01100011 !emit { modrm(); mem(size => 8); }
 PACKSSWB        SSE2    00001111 01100011 !emit { data16(); modrm(); mem(size => 16, align => 16); }
@@ -285,6 +321,8 @@ UNPCKLPD        SSE2    00001111 00010100 !emit { data16(); modrm(); mem(size =>
 UNPCKHPS        SSE     00001111 00010101 !emit { modrm(); mem(size => 16, align => 16); }
 UNPCKHPD        SSE2    00001111 00010101 !emit { data16(); modrm(); mem(size => 16, align => 16); }
 
+PSHUFB_64       SSSE3   00001111 00111000 00000000 !emit { modrm(); mem(size => 8); }
+PSHUFB          SSSE3   00001111 00111000 00000000 !emit { data16(); modrm(); mem(size => 16, align => 16); }
 PSHUFW          SSE     00001111 01110000 !emit { modrm(); mem(size => 8); imm(size => 1); }
 PSHUFLW         SSE2    00001111 01110000 !emit { repne(); modrm(); mem(size => 16, align => 16); imm(size => 1); }
 PSHUFHW         SSE2    00001111 01110000 !emit { rep(); modrm(); mem(size => 16, align => 16); imm(size => 1); }
-- 
2.20.1



  parent reply	other threads:[~2019-07-01  4:43 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-01  4:35 [Qemu-devel] [RISU RFC PATCH v2 00/14] Support for generating x86 MMX/SSE/AVX test images Jan Bobek
2019-07-01  4:35 ` [Qemu-devel] [RISU RFC PATCH v2 01/14] risugen_common: add insnv, randint_constr, rand_fill Jan Bobek
2019-07-03 15:22   ` Richard Henderson
2019-07-10 17:48     ` Jan Bobek
2019-07-01  4:35 ` [Qemu-devel] [RISU RFC PATCH v2 02/14] risugen_x86_asm: add module Jan Bobek
2019-07-03 15:37   ` Richard Henderson
2019-07-10 18:02     ` Jan Bobek
2019-07-01  4:35 ` [Qemu-devel] [RISU RFC PATCH v2 03/14] risugen_x86_emit: " Jan Bobek
2019-07-03 15:47   ` Richard Henderson
2019-07-10 18:08     ` Jan Bobek
2019-07-01  4:35 ` [Qemu-devel] [RISU RFC PATCH v2 04/14] risugen_x86: " Jan Bobek
2019-07-03 16:11   ` Richard Henderson
2019-07-10 18:21     ` Jan Bobek
2019-07-11  9:26       ` Richard Henderson
2019-07-11 13:10         ` Jan Bobek
2019-07-01  4:35 ` [Qemu-devel] [RISU RFC PATCH v2 05/14] risugen: allow all byte-aligned instructions Jan Bobek
2019-07-01  4:35 ` [Qemu-devel] [RISU RFC PATCH v2 06/14] x86.risu: add MMX instructions Jan Bobek
2019-07-03 21:35   ` Richard Henderson
2019-07-10 18:29     ` Jan Bobek
2019-07-11  9:32       ` Richard Henderson
2019-07-11 13:29         ` Jan Bobek
2019-07-11 13:57           ` Richard Henderson
2019-07-11 21:29             ` Jan Bobek
2019-07-03 21:49   ` Richard Henderson
2019-07-10 18:32     ` Jan Bobek
2019-07-11  9:34       ` Richard Henderson
2019-07-11  9:44         ` Alex Bennée
2019-07-03 22:01   ` Peter Maydell
2019-07-10 18:35     ` Jan Bobek
2019-07-11  6:45       ` Alex Bennée
2019-07-11 13:33         ` Jan Bobek
2019-07-01  4:35 ` [Qemu-devel] [RISU RFC PATCH v2 07/14] x86.risu: add SSE instructions Jan Bobek
2019-07-01  4:35 ` [Qemu-devel] [RISU RFC PATCH v2 08/14] x86.risu: add SSE2 instructions Jan Bobek
2019-07-01  4:35 ` [Qemu-devel] [RISU RFC PATCH v2 09/14] x86.risu: add SSE3 instructions Jan Bobek
2019-07-01  4:35 ` Jan Bobek [this message]
2019-07-01  4:35 ` [Qemu-devel] [RISU RFC PATCH v2 11/14] x86.risu: add SSE4.1 and SSE4.2 instructions Jan Bobek
2019-07-01  4:35 ` [Qemu-devel] [RISU RFC PATCH v2 13/14] x86.risu: add AVX instructions Jan Bobek
2019-07-01  4:35 ` [Qemu-devel] [RISU RFC PATCH v2 14/14] x86.risu: add AVX2 instructions Jan Bobek

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