From: Jan Bobek <jan.bobek@gmail.com>
To: qemu-devel@nongnu.org
Cc: "Jan Bobek" <jan.bobek@gmail.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Richard Henderson" <richard.henderson@linaro.org>
Subject: [Qemu-devel] [RISU RFC PATCH v2 07/14] x86.risu: add SSE instructions
Date: Mon, 1 Jul 2019 00:35:29 -0400 [thread overview]
Message-ID: <20190701043536.26019-8-jan.bobek@gmail.com> (raw)
In-Reply-To: <20190701043536.26019-1-jan.bobek@gmail.com>
Add SSE instructions to the x86 configuration file.
Signed-off-by: Jan Bobek <jan.bobek@gmail.com>
---
x86.risu | 100 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 100 insertions(+)
diff --git a/x86.risu b/x86.risu
index f2dd9b0..c29b210 100644
--- a/x86.risu
+++ b/x86.risu
@@ -19,6 +19,18 @@ MOVQ MMX 00001111 011 d 1110 !emit { rex(w => 1); modrm(mod => MO
MOVQ_mem MMX 00001111 011 d 1110 !emit { rex(w => 1); modrm(mod => ~MOD_DIRECT); mem(size => 8); }
MOVQ_mm MMX 00001111 011 d 1111 !emit { modrm(); mem(size => 8); }
+MOVAPS SSE 00001111 0010100 d !emit { modrm(); mem(size => 16, align => 16); }
+MOVUPS SSE 00001111 0001000 d !emit { modrm(); mem(size => 16); }
+MOVSS SSE 00001111 0001000 d !emit { rep(); modrm(); mem(size => 4); }
+
+MOVLPS SSE 00001111 0001001 d !emit { modrm(mod => ~MOD_DIRECT); mem(size => 8); }
+MOVHPS SSE 00001111 0001011 d !emit { modrm(mod => ~MOD_DIRECT); mem(size => 8); }
+MOVLHPS SSE 00001111 00010110 !emit { modrm(mod => MOD_DIRECT); }
+MOVHLPS SSE 00001111 00010010 !emit { modrm(mod => MOD_DIRECT); }
+
+PMOVMSKB SSE 00001111 11010111 !emit { modrm(mod => MOD_DIRECT, reg => ~REG_ESP); }
+MOVMSKPS SSE 00001111 01010000 !emit { modrm(mod => MOD_DIRECT, reg => ~REG_ESP); }
+
# Arithmetic Instructions
PADDB MMX 00001111 11111100 !emit { modrm(); mem(size => 8); }
PADDW MMX 00001111 11111101 !emit { modrm(); mem(size => 8); }
@@ -29,6 +41,9 @@ PADDSW MMX 00001111 11101101 !emit { modrm(); mem(size => 8); }
PADDUSB MMX 00001111 11011100 !emit { modrm(); mem(size => 8); }
PADDUSW MMX 00001111 11011101 !emit { modrm(); mem(size => 8); }
+ADDPS SSE 00001111 01011000 !emit { modrm(); mem(size => 16, align => 16); }
+ADDSS SSE 00001111 01011000 !emit { rep(); modrm(); mem(size => 4); }
+
PSUBB MMX 00001111 11111000 !emit { modrm(); mem(size => 8); }
PSUBW MMX 00001111 11111001 !emit { modrm(); mem(size => 8); }
PSUBD MMX 00001111 11111010 !emit { modrm(); mem(size => 8); }
@@ -37,11 +52,47 @@ PSUBSW MMX 00001111 11101001 !emit { modrm(); mem(size => 8); }
PSUBUSB MMX 00001111 11011000 !emit { modrm(); mem(size => 8); }
PSUBUSW MMX 00001111 11011001 !emit { modrm(); mem(size => 8); }
+SUBPS SSE 00001111 01011100 !emit { modrm(); mem(size => 16, align => 16); }
+SUBSS SSE 00001111 01011100 !emit { rep(); modrm(); mem(size => 4); }
+
PMULLW MMX 00001111 11010101 !emit { modrm(); mem(size => 8); }
PMULHW MMX 00001111 11100101 !emit { modrm(); mem(size => 8); }
+PMULHUW SSE 00001111 11100100 !emit { modrm(); mem(size => 8); }
+
+MULPS SSE 00001111 01011001 !emit { modrm(); mem(size => 16, align => 16); }
+MULSS SSE 00001111 01011001 !emit { rep(); modrm(); mem(size => 4); }
PMADDWD MMX 00001111 11110101 !emit { modrm(); mem(size => 8); }
+DIVPS SSE 00001111 01011110 !emit { modrm(); mem(size => 16, align => 16); }
+DIVSS SSE 00001111 01011110 !emit { rep(); modrm(); mem(size => 4); }
+
+RCPPS SSE 00001111 01010011 !emit { modrm(); mem(size => 16, align => 16); }
+RCPSS SSE 00001111 01010011 !emit { rep(); modrm(); mem(size => 4); }
+
+SQRTPS SSE 00001111 01010001 !emit { modrm(); mem(size => 16, align => 16); }
+SQRTSS SSE 00001111 01010001 !emit { rep(); modrm(); mem(size => 4); }
+
+RSQRTPS SSE 00001111 01010010 !emit { modrm(); mem(size => 16, align => 16); }
+RSQRTSS SSE 00001111 01010010 !emit { rep(); modrm(); mem(size => 4); }
+
+PMINUB SSE 00001111 11011010 !emit { modrm(); mem(size => 8); }
+PMINSW SSE 00001111 11101010 !emit { modrm(); mem(size => 8); }
+
+MINPS SSE 00001111 01011101 !emit { modrm(); mem(size => 16, align => 16); }
+MINSS SSE 00001111 01011101 !emit { rep(); modrm(); mem(size => 4); }
+
+PMAXUB SSE 00001111 11011110 !emit { modrm(); mem(size => 8); }
+PMAXSW SSE 00001111 11101110 !emit { modrm(); mem(size => 8); }
+
+MAXPS SSE 00001111 01011111 !emit { modrm(); mem(size => 16, align => 16); }
+MAXSS SSE 00001111 01011111 !emit { rep(); modrm(); mem(size => 4); }
+
+PAVGB SSE 00001111 11100000 !emit { modrm(); mem(size => 8); }
+PAVGW SSE 00001111 11100011 !emit { modrm(); mem(size => 8); }
+
+PSADBW SSE 00001111 11110110 !emit { modrm(); mem(size => 8); }
+
# Comparison Instructions
PCMPEQB MMX 00001111 01110100 !emit { modrm(); mem(size => 8); }
PCMPEQW MMX 00001111 01110101 !emit { modrm(); mem(size => 8); }
@@ -50,11 +101,24 @@ PCMPGTB MMX 00001111 01100100 !emit { modrm(); mem(size => 8); }
PCMPGTW MMX 00001111 01100101 !emit { modrm(); mem(size => 8); }
PCMPGTD MMX 00001111 01100110 !emit { modrm(); mem(size => 8); }
+CMPPS SSE 00001111 11000010 !emit { modrm(); mem(size => 16, align => 16); imm(size => 1); }
+CMPSS SSE 00001111 11000010 !emit { rep(); modrm(); mem(size => 4); imm(size => 1); }
+
+UCOMISS SSE 00001111 00101110 !emit { modrm(); mem(size => 4); }
+COMISS SSE 00001111 00101111 !emit { modrm(); mem(size => 4); }
+
# Logical Instructions
PAND MMX 00001111 11011011 !emit { modrm(); mem(size => 8); }
+ANDPS SSE 00001111 01010100 !emit { modrm(); mem(size => 16, align => 16); }
+
PANDN MMX 00001111 11011111 !emit { modrm(); mem(size => 8); }
+ANDNPS SSE 00001111 01010101 !emit { modrm(); mem(size => 16, align => 16); }
+
POR MMX 00001111 11101011 !emit { modrm(); mem(size => 8); }
+ORPS SSE 00001111 01010110 !emit { modrm(); mem(size => 16, align => 16); }
+
PXOR MMX 00001111 11101111 !emit { modrm(); mem(size => 8); }
+XORPS SSE 00001111 01010111 !emit { modrm(); mem(size => 16, align => 16); }
# Shift and Rotate Instructions
PSLLW MMX 00001111 11110001 !emit { modrm(); mem(size => 8); }
@@ -92,5 +156,41 @@ PUNPCKLBW MMX 00001111 01100000 !emit { modrm(); mem(size => 4); }
PUNPCKLWD MMX 00001111 01100001 !emit { modrm(); mem(size => 4); }
PUNPCKLDQ MMX 00001111 01100010 !emit { modrm(); mem(size => 4); }
+UNPCKLPS SSE 00001111 00010100 !emit { modrm(); mem(size => 16, align => 16); }
+UNPCKHPS SSE 00001111 00010101 !emit { modrm(); mem(size => 16, align => 16); }
+
+PSHUFW SSE 00001111 01110000 !emit { modrm(); mem(size => 8); imm(size => 1); }
+SHUFPS SSE 00001111 11000110 !emit { modrm(); mem(size => 16, align => 16); imm(size => 1); }
+
+PINSRW SSE 00001111 11000100 !emit { modrm(); mem(size => 2); imm(size => 1); }
+PEXTRW_reg SSE 00001111 11000101 !emit { modrm(mod => MOD_DIRECT, reg => ~REG_ESP); imm(size => 1); }
+
+# Conversion Instructions
+CVTPI2PS SSE 00001111 00101010 !emit { modrm(); mem(size => 8); }
+CVTSI2SS SSE 00001111 00101010 !emit { rep(); modrm(); mem(size => 4); }
+CVTSI2SS_64 SSE 00001111 00101010 !emit { rep(); rex(w => 1); modrm(); mem(size => 8); }
+
+CVTPS2PI SSE 00001111 00101101 !emit { modrm(); mem(size => 8); }
+CVTSS2SI SSE 00001111 00101101 !emit { rep(); modrm(reg => ~REG_ESP); mem(size => 4); }
+CVTSS2SI_64 SSE 00001111 00101101 !emit { rep(); rex(w => 1); modrm(reg => ~REG_ESP); mem(size => 4); }
+
+CVTTPS2PI SSE 00001111 00101100 !emit { modrm(); mem(size => 8); }
+CVTTSS2SI SSE 00001111 00101100 !emit { rep(); modrm(reg => ~REG_ESP); mem(size => 4); }
+CVTTSS2SI_64 SSE 00001111 00101100 !emit { rep(); rex(w => 1); modrm(reg => ~REG_ESP); mem(size => 4); }
+
+# Cacheability Control, Prefetch, and Instruction Ordering Instructions
+MASKMOVQ SSE 00001111 11110111 !emit { modrm(mod => MOD_DIRECT); mem(size => 8, base => REG_EDI); }
+MOVNTPS SSE 00001111 00101011 !emit { modrm(mod => ~MOD_DIRECT); mem(size => 16, align => 16); }
+MOVNTQ SSE 00001111 11100111 !emit { modrm(mod => ~MOD_DIRECT); mem(size => 8); }
+
+PREFETCHT0 SSE 00001111 00011000 !emit { modrm(mod => ~MOD_DIRECT, reg => 1); mem(size => 1); }
+PREFETCHT1 SSE 00001111 00011000 !emit { modrm(mod => ~MOD_DIRECT, reg => 2); mem(size => 1); }
+PREFETCHT2 SSE 00001111 00011000 !emit { modrm(mod => ~MOD_DIRECT, reg => 3); mem(size => 1); }
+PREFETCHNTA SSE 00001111 00011000 !emit { modrm(mod => ~MOD_DIRECT, reg => 0); mem(size => 1); }
+SFENCE SSE 00001111 10101110 !emit { modrm(mod => MOD_DIRECT, reg => 7); }
+
# State Management Instructions
EMMS MMX 00001111 01110111 !emit { }
+
+# LDMXCSR SSE 00001111 10101110 !emit { modrm(mod => ~MOD_DIRECT, reg => 2); mem(size => 4); }
+STMXCSR SSE 00001111 10101110 !emit { modrm(mod => ~MOD_DIRECT, reg => 3); mem(size => 4); }
--
2.20.1
next prev parent reply other threads:[~2019-07-01 4:43 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-01 4:35 [Qemu-devel] [RISU RFC PATCH v2 00/14] Support for generating x86 MMX/SSE/AVX test images Jan Bobek
2019-07-01 4:35 ` [Qemu-devel] [RISU RFC PATCH v2 01/14] risugen_common: add insnv, randint_constr, rand_fill Jan Bobek
2019-07-03 15:22 ` Richard Henderson
2019-07-10 17:48 ` Jan Bobek
2019-07-01 4:35 ` [Qemu-devel] [RISU RFC PATCH v2 02/14] risugen_x86_asm: add module Jan Bobek
2019-07-03 15:37 ` Richard Henderson
2019-07-10 18:02 ` Jan Bobek
2019-07-01 4:35 ` [Qemu-devel] [RISU RFC PATCH v2 03/14] risugen_x86_emit: " Jan Bobek
2019-07-03 15:47 ` Richard Henderson
2019-07-10 18:08 ` Jan Bobek
2019-07-01 4:35 ` [Qemu-devel] [RISU RFC PATCH v2 04/14] risugen_x86: " Jan Bobek
2019-07-03 16:11 ` Richard Henderson
2019-07-10 18:21 ` Jan Bobek
2019-07-11 9:26 ` Richard Henderson
2019-07-11 13:10 ` Jan Bobek
2019-07-01 4:35 ` [Qemu-devel] [RISU RFC PATCH v2 05/14] risugen: allow all byte-aligned instructions Jan Bobek
2019-07-01 4:35 ` [Qemu-devel] [RISU RFC PATCH v2 06/14] x86.risu: add MMX instructions Jan Bobek
2019-07-03 21:35 ` Richard Henderson
2019-07-10 18:29 ` Jan Bobek
2019-07-11 9:32 ` Richard Henderson
2019-07-11 13:29 ` Jan Bobek
2019-07-11 13:57 ` Richard Henderson
2019-07-11 21:29 ` Jan Bobek
2019-07-03 21:49 ` Richard Henderson
2019-07-10 18:32 ` Jan Bobek
2019-07-11 9:34 ` Richard Henderson
2019-07-11 9:44 ` Alex Bennée
2019-07-03 22:01 ` Peter Maydell
2019-07-10 18:35 ` Jan Bobek
2019-07-11 6:45 ` Alex Bennée
2019-07-11 13:33 ` Jan Bobek
2019-07-01 4:35 ` Jan Bobek [this message]
2019-07-01 4:35 ` [Qemu-devel] [RISU RFC PATCH v2 08/14] x86.risu: add SSE2 instructions Jan Bobek
2019-07-01 4:35 ` [Qemu-devel] [RISU RFC PATCH v2 09/14] x86.risu: add SSE3 instructions Jan Bobek
2019-07-01 4:35 ` [Qemu-devel] [RISU RFC PATCH v2 10/14] x86.risu: add SSSE3 instructions Jan Bobek
2019-07-01 4:35 ` [Qemu-devel] [RISU RFC PATCH v2 11/14] x86.risu: add SSE4.1 and SSE4.2 instructions Jan Bobek
2019-07-01 4:35 ` [Qemu-devel] [RISU RFC PATCH v2 13/14] x86.risu: add AVX instructions Jan Bobek
2019-07-01 4:35 ` [Qemu-devel] [RISU RFC PATCH v2 14/14] x86.risu: add AVX2 instructions Jan Bobek
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