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From: Animesh Manna <animesh.manna@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@intel.com>
Subject: [PATCH 14/15] drm/i915/dsb: Documentation for DSB.
Date: Mon,  1 Jul 2019 11:56:31 +0530	[thread overview]
Message-ID: <20190701062632.456-15-animesh.manna@intel.com> (raw)
In-Reply-To: <20190701062632.456-1-animesh.manna@intel.com>

Added docbook info regarding Display State Buffer(DSB) which
is added from gen12 onwards to batch submit display HW programming.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 Documentation/gpu/i915.rst       |  9 ++++++
 drivers/gpu/drm/i915/intel_dsb.c | 54 ++++++++++++++++++++++++++++++++
 2 files changed, 63 insertions(+)

diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index c38ef0dda605..c5bd804eca55 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -249,6 +249,15 @@ Display PLLs
 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.h
    :internal:
 
+Display State Buffer
+--------------------
+
+.. kernel-doc:: drivers/gpu/drm/i915/intel_dsb.c
+   :doc: DSB
+
+.. kernel-doc:: drivers/gpu/drm/i915/intel_dsb.c
+   :internal:
+
 Memory Management and Command Submission
 ========================================
 
diff --git a/drivers/gpu/drm/i915/intel_dsb.c b/drivers/gpu/drm/i915/intel_dsb.c
index dddaae27d7b5..b74126c99a16 100644
--- a/drivers/gpu/drm/i915/intel_dsb.c
+++ b/drivers/gpu/drm/i915/intel_dsb.c
@@ -8,6 +8,23 @@
 
 #define DSB_BUF_SIZE    (2 * PAGE_SIZE)
 
+/**
+ * DOC: DSB
+ *
+ * A DSB (Display State Buffer) is a queue of MMIO instructions in the memory
+ * which can be offloaded to DSB HW in Display Controller. DSB HW is a DMA
+ * engine that can be programmed to download the DSB from memory.
+ * It allows driver to batch submit display HW programming. This helps to
+ * reduce loading time and CPU activity, thereby making the context switch
+ * faster. DSB Support added from Gen12 Intel graphics based platform.
+ *
+ * DSB's can access only the pipe, plane, and transcoder Data Island Packet
+ * registers.
+ *
+ * DSB HW can support only register writes (both indexed and direct MMIO
+ * writes). There are no registers reads possible with DSB HW engine.
+ */
+
 /* DSB opcodes. */
 #define DSB_OPCODE_SHIFT		24
 #define DSB_OPCODE_NOOP			0x0
@@ -72,6 +89,17 @@ static bool intel_dsb_disable_engine(struct intel_dsb *dsb)
 	return true;
 }
 
+/**
+ * intel_dsb_get() - Allocate dsb context and return a dsb instance.
+ * @crtc: intel_crtc structure to get pipe info.
+ *
+ * This function will give handle of the DSB instance which
+ * user want to operate on.
+ *
+ * Return : address of Intel_dsb instance requested for.
+ * In failure case, the dsb instance will not have any command buffer.
+ */
+
 struct intel_dsb *
 intel_dsb_get(struct intel_crtc *crtc)
 {
@@ -164,6 +192,18 @@ static void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
 		buf[dsb->free_pos] = 0;
 }
 
+/**
+ * intel_dsb_reg_write() -Write to the dsb context for normal
+ * register.
+ * @dsb: intel_dsb structure.
+ * @reg: register address.
+ * @val: value.
+ *
+ * This function is used for writing register-value pair in command
+ * buffer of DSB. During command buffer overflow, a warning
+ * is thrown and rest all erroneous condition register programming is done
+ * through mmio write.
+ */
 void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
 {
 	struct intel_crtc *crtc = dsb->crtc;
@@ -191,6 +231,13 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
 				i915_mmio_reg_offset(reg);
 }
 
+/**
+ * intel_dsb_commit() - Trigger workload execution of DSB.
+ * @dsb: intel_dsb structure.
+ *
+ * This function is used to do actual write to hardware using DSB.
+ * On errors, fall back to MMIO. Also this function help to reset the context.
+ */
 void intel_dsb_commit(struct intel_dsb *dsb)
 {
 	struct intel_crtc *crtc = dsb->crtc;
@@ -234,6 +281,13 @@ void intel_dsb_commit(struct intel_dsb *dsb)
 	intel_dsb_disable_engine(dsb);
 }
 
+/**
+ * intel_dsb_put() - To destroy DSB context.
+ * @dsb: intel_dsb structure.
+ *
+ * This function is used to destroy the dsb-context by doing unpin
+ * and release the vma object.
+ */
 void intel_dsb_put(struct intel_dsb *dsb)
 {
 	struct intel_crtc *crtc = dsb->crtc;
-- 
2.21.0

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  parent reply	other threads:[~2019-07-01  6:34 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-01  6:26 [PATCH 00/15] DSB enablement Animesh Manna
2019-07-01  6:26 ` [PATCH 01/15] drm/i915/dsb: feature flag added for display state buffer Animesh Manna
2019-07-01  6:26 ` [PATCH 02/15] drm/i915/dsb: DSB context creation Animesh Manna
2019-07-01  6:26 ` [PATCH 03/15] drm/i915/dsb: single register write function for DSB Animesh Manna
2019-07-01  6:26 ` [PATCH 04/15] drm/i915/dsb: Added enum for reg write capability Animesh Manna
2019-07-01  6:26 ` [PATCH 05/15] drm/i915/dsb: Indexed register write function for DSB Animesh Manna
2019-07-01  6:26 ` [PATCH 06/15] drm/i915/dsb: Update i915_write to call dsb-write Animesh Manna
2019-07-01  6:26 ` [PATCH 07/15] drm/i915/dsb: Register definition of DSB registers Animesh Manna
2019-07-01  6:26 ` [PATCH 08/15] drm/i915/dsb: Check DSB engine status Animesh Manna
2019-07-01  6:26 ` [PATCH 09/15] drm/i915/dsb: functions to enable/disable DSB engine Animesh Manna
2019-07-01  6:26 ` [PATCH 10/15] drm/i915/dsb: function to trigger workload execution of DSB Animesh Manna
2019-07-01  6:26 ` [PATCH 11/15] drm/i915/dsb: function to destroy DSB context Animesh Manna
2019-07-01  6:26 ` [PATCH 12/15] drm/i915/dsb: Early prepare of dsb context Animesh Manna
2019-07-01  6:26 ` [PATCH 13/15] drm/i915/dsb: Cleanup of DSB context Animesh Manna
2019-07-01  6:26 ` Animesh Manna [this message]
2019-07-01  6:26 ` [PATCH 15/15] drm/i915/dsb: Enable gamma lut programming using DSB Animesh Manna
2019-07-01  7:09 ` ✗ Fi.CI.CHECKPATCH: warning for DSB enablement Patchwork
2019-07-01  7:16 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-07-01  7:39 ` ✓ Fi.CI.BAT: success " Patchwork
2019-07-01  9:05 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-08-09  9:42 ` [PATCH 00/15] " Jani Nikula
2019-08-12  8:52   ` Animesh Manna

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