From: Vidya Sagar <vidyas@nvidia.com>
To: lorenzo.pieralisi@arm.com, bhelgaas@google.com,
robh+dt@kernel.org, mark.rutland@arm.com,
thierry.reding@gmail.com, jonathanh@nvidia.com, kishon@ti.com,
catalin.marinas@arm.com, will.deacon@arm.com,
jingoohan1@gmail.com, gustavo.pimentel@synopsys.com
Cc: digetx@gmail.com, mperttunen@nvidia.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, kthota@nvidia.com,
mmaddireddy@nvidia.com, vidyas@nvidia.com, sagar.tv@gmail.com
Subject: [PATCH V12 01/12] PCI: Add #defines for some of PCIe spec r4.0 features
Date: Mon, 1 Jul 2019 18:09:59 +0530 [thread overview]
Message-ID: <20190701124010.7484-2-vidyas@nvidia.com> (raw)
In-Reply-To: <20190701124010.7484-1-vidyas@nvidia.com>
Add #defines only for the Data Link Feature and Physical Layer 16.0 GT/s
features.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
---
Changes since [v11]:
* None
Changes since [v10]:
* None
Changes since [v9]:
* None
Changes since [v8]:
* None
Changes since [v7]:
* None
Changes since [v6]:
* None
Changes since [v5]:
* None
Changes since [v4]:
* None
Changes since [v3]:
* None
Changes since [v2]:
* Updated commit message and description to explicitly mention that defines are
added only for some of the features and not all.
Changes since [v1]:
* None
include/uapi/linux/pci_regs.h | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index f28e562d7ca8..1c79f6a097d2 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -713,7 +713,9 @@
#define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */
#define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */
#define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */
-#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM
+#define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */
+#define PCI_EXT_CAP_ID_PL 0x26 /* Physical Layer 16.0 GT/s */
+#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL
#define PCI_EXT_CAP_DSN_SIZEOF 12
#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
@@ -1053,4 +1055,22 @@
#define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */
#define PCI_L1SS_CTL2 0x0c /* Control 2 Register */
+/* Data Link Feature */
+#define PCI_DLF_CAP 0x04 /* Capabilities Register */
+#define PCI_DLF_LOCAL_DLF_SUP_MASK 0x007fffff /* Local Data Link Feature Supported */
+#define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */
+#define PCI_DLF_STS 0x08 /* Status Register */
+#define PCI_DLF_REMOTE_DLF_SUP_MASK 0x007fffff /* Remote Data Link Feature Supported */
+#define PCI_DLF_REMOTE_DLF_SUP_VALID 0x80000000 /* Remote Data Link Feature Support Valid */
+
+/* Physical Layer 16.0 GT/s */
+#define PCI_PL_16GT_CAP 0x04 /* Capabilities Register */
+#define PCI_PL_16GT_CTRL 0x08 /* Control Register */
+#define PCI_PL_16GT_STS 0x0c /* Status Register */
+#define PCI_PL_16GT_LDPM_STS 0x10 /* Local Data Parity Mismatch Status Register */
+#define PCI_PL_16GT_FRDPM_STS 0x14 /* First Retimer Data Parity Mismatch Status Register */
+#define PCI_PL_16GT_SRDPM_STS 0x18 /* Second Retimer Data Parity Mismatch Status Register */
+#define PCI_PL_16GT_RSVD 0x1C /* Reserved */
+#define PCI_PL_16GT_LE_CTRL 0x20 /* Lane Equalization Control Register */
+
#endif /* LINUX_PCI_REGS_H */
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Vidya Sagar <vidyas@nvidia.com>
To: <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
<robh+dt@kernel.org>, <mark.rutland@arm.com>,
<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
<kishon@ti.com>, <catalin.marinas@arm.com>, <will.deacon@arm.com>,
<jingoohan1@gmail.com>, <gustavo.pimentel@synopsys.com>
Cc: <digetx@gmail.com>, <mperttunen@nvidia.com>,
<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <kthota@nvidia.com>,
<mmaddireddy@nvidia.com>, <vidyas@nvidia.com>,
<sagar.tv@gmail.com>
Subject: [PATCH V12 01/12] PCI: Add #defines for some of PCIe spec r4.0 features
Date: Mon, 1 Jul 2019 18:09:59 +0530 [thread overview]
Message-ID: <20190701124010.7484-2-vidyas@nvidia.com> (raw)
In-Reply-To: <20190701124010.7484-1-vidyas@nvidia.com>
Add #defines only for the Data Link Feature and Physical Layer 16.0 GT/s
features.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
---
Changes since [v11]:
* None
Changes since [v10]:
* None
Changes since [v9]:
* None
Changes since [v8]:
* None
Changes since [v7]:
* None
Changes since [v6]:
* None
Changes since [v5]:
* None
Changes since [v4]:
* None
Changes since [v3]:
* None
Changes since [v2]:
* Updated commit message and description to explicitly mention that defines are
added only for some of the features and not all.
Changes since [v1]:
* None
include/uapi/linux/pci_regs.h | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index f28e562d7ca8..1c79f6a097d2 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -713,7 +713,9 @@
#define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */
#define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */
#define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */
-#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM
+#define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */
+#define PCI_EXT_CAP_ID_PL 0x26 /* Physical Layer 16.0 GT/s */
+#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL
#define PCI_EXT_CAP_DSN_SIZEOF 12
#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
@@ -1053,4 +1055,22 @@
#define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */
#define PCI_L1SS_CTL2 0x0c /* Control 2 Register */
+/* Data Link Feature */
+#define PCI_DLF_CAP 0x04 /* Capabilities Register */
+#define PCI_DLF_LOCAL_DLF_SUP_MASK 0x007fffff /* Local Data Link Feature Supported */
+#define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */
+#define PCI_DLF_STS 0x08 /* Status Register */
+#define PCI_DLF_REMOTE_DLF_SUP_MASK 0x007fffff /* Remote Data Link Feature Supported */
+#define PCI_DLF_REMOTE_DLF_SUP_VALID 0x80000000 /* Remote Data Link Feature Support Valid */
+
+/* Physical Layer 16.0 GT/s */
+#define PCI_PL_16GT_CAP 0x04 /* Capabilities Register */
+#define PCI_PL_16GT_CTRL 0x08 /* Control Register */
+#define PCI_PL_16GT_STS 0x0c /* Status Register */
+#define PCI_PL_16GT_LDPM_STS 0x10 /* Local Data Parity Mismatch Status Register */
+#define PCI_PL_16GT_FRDPM_STS 0x14 /* First Retimer Data Parity Mismatch Status Register */
+#define PCI_PL_16GT_SRDPM_STS 0x18 /* Second Retimer Data Parity Mismatch Status Register */
+#define PCI_PL_16GT_RSVD 0x1C /* Reserved */
+#define PCI_PL_16GT_LE_CTRL 0x20 /* Lane Equalization Control Register */
+
#endif /* LINUX_PCI_REGS_H */
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Vidya Sagar <vidyas@nvidia.com>
To: <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
<robh+dt@kernel.org>, <mark.rutland@arm.com>,
<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
<kishon@ti.com>, <catalin.marinas@arm.com>, <will.deacon@arm.com>,
<jingoohan1@gmail.com>, <gustavo.pimentel@synopsys.com>
Cc: devicetree@vger.kernel.org, mmaddireddy@nvidia.com,
kthota@nvidia.com, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, mperttunen@nvidia.com,
linux-tegra@vger.kernel.org, digetx@gmail.com, vidyas@nvidia.com,
linux-arm-kernel@lists.infradead.org, sagar.tv@gmail.com
Subject: [PATCH V12 01/12] PCI: Add #defines for some of PCIe spec r4.0 features
Date: Mon, 1 Jul 2019 18:09:59 +0530 [thread overview]
Message-ID: <20190701124010.7484-2-vidyas@nvidia.com> (raw)
In-Reply-To: <20190701124010.7484-1-vidyas@nvidia.com>
Add #defines only for the Data Link Feature and Physical Layer 16.0 GT/s
features.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
---
Changes since [v11]:
* None
Changes since [v10]:
* None
Changes since [v9]:
* None
Changes since [v8]:
* None
Changes since [v7]:
* None
Changes since [v6]:
* None
Changes since [v5]:
* None
Changes since [v4]:
* None
Changes since [v3]:
* None
Changes since [v2]:
* Updated commit message and description to explicitly mention that defines are
added only for some of the features and not all.
Changes since [v1]:
* None
include/uapi/linux/pci_regs.h | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index f28e562d7ca8..1c79f6a097d2 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -713,7 +713,9 @@
#define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */
#define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */
#define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */
-#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM
+#define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */
+#define PCI_EXT_CAP_ID_PL 0x26 /* Physical Layer 16.0 GT/s */
+#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL
#define PCI_EXT_CAP_DSN_SIZEOF 12
#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
@@ -1053,4 +1055,22 @@
#define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */
#define PCI_L1SS_CTL2 0x0c /* Control 2 Register */
+/* Data Link Feature */
+#define PCI_DLF_CAP 0x04 /* Capabilities Register */
+#define PCI_DLF_LOCAL_DLF_SUP_MASK 0x007fffff /* Local Data Link Feature Supported */
+#define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */
+#define PCI_DLF_STS 0x08 /* Status Register */
+#define PCI_DLF_REMOTE_DLF_SUP_MASK 0x007fffff /* Remote Data Link Feature Supported */
+#define PCI_DLF_REMOTE_DLF_SUP_VALID 0x80000000 /* Remote Data Link Feature Support Valid */
+
+/* Physical Layer 16.0 GT/s */
+#define PCI_PL_16GT_CAP 0x04 /* Capabilities Register */
+#define PCI_PL_16GT_CTRL 0x08 /* Control Register */
+#define PCI_PL_16GT_STS 0x0c /* Status Register */
+#define PCI_PL_16GT_LDPM_STS 0x10 /* Local Data Parity Mismatch Status Register */
+#define PCI_PL_16GT_FRDPM_STS 0x14 /* First Retimer Data Parity Mismatch Status Register */
+#define PCI_PL_16GT_SRDPM_STS 0x18 /* Second Retimer Data Parity Mismatch Status Register */
+#define PCI_PL_16GT_RSVD 0x1C /* Reserved */
+#define PCI_PL_16GT_LE_CTRL 0x20 /* Lane Equalization Control Register */
+
#endif /* LINUX_PCI_REGS_H */
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-07-01 12:39 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-01 12:39 [PATCH V12 00/12] Add Tegra194 PCIe support Vidya Sagar
2019-07-01 12:39 ` Vidya Sagar
2019-07-01 12:39 ` Vidya Sagar
2019-07-01 12:39 ` Vidya Sagar [this message]
2019-07-01 12:39 ` [PATCH V12 01/12] PCI: Add #defines for some of PCIe spec r4.0 features Vidya Sagar
2019-07-01 12:39 ` Vidya Sagar
2019-07-05 13:46 ` Vidya Sagar
2019-07-05 13:46 ` Vidya Sagar
2019-07-05 13:46 ` Vidya Sagar
2019-07-09 13:38 ` Vidya Sagar
2019-07-09 13:38 ` Vidya Sagar
2019-07-09 13:38 ` Vidya Sagar
2019-07-09 14:14 ` Bjorn Helgaas
2019-07-09 14:14 ` Bjorn Helgaas
2019-07-10 5:18 ` Vidya Sagar
2019-07-10 5:18 ` Vidya Sagar
2019-07-10 5:18 ` Vidya Sagar
2019-07-01 12:40 ` [PATCH V12 02/12] PCI: Disable MSI for Tegra root ports Vidya Sagar
2019-07-01 12:40 ` Vidya Sagar
2019-07-01 12:40 ` Vidya Sagar
2019-07-01 12:40 ` [PATCH V12 03/12] PCI: dwc: Perform dbi regs write lock towards the end Vidya Sagar
2019-07-01 12:40 ` Vidya Sagar
2019-07-01 12:40 ` Vidya Sagar
2019-07-01 12:40 ` [PATCH V12 04/12] PCI: dwc: Move config space capability search API Vidya Sagar
2019-07-01 12:40 ` Vidya Sagar
2019-07-01 12:40 ` Vidya Sagar
2019-07-01 12:40 ` [PATCH V12 05/12] PCI: dwc: Add ext " Vidya Sagar
2019-07-01 12:40 ` Vidya Sagar
2019-07-01 12:40 ` Vidya Sagar
2019-07-01 12:40 ` [PATCH V12 06/12] dt-bindings: PCI: designware: Add binding for CDM register check Vidya Sagar
2019-07-01 12:40 ` Vidya Sagar
2019-07-01 12:40 ` Vidya Sagar
2019-07-01 12:40 ` [PATCH V12 07/12] PCI: dwc: Add support to enable " Vidya Sagar
2019-07-01 12:40 ` Vidya Sagar
2019-07-01 12:40 ` Vidya Sagar
2019-07-01 12:40 ` [PATCH V12 08/12] dt-bindings: Add PCIe supports-clkreq property Vidya Sagar
2019-07-01 12:40 ` Vidya Sagar
2019-07-01 12:40 ` Vidya Sagar
2019-07-01 12:40 ` [PATCH V12 09/12] dt-bindings: PCI: tegra: Add device tree support for Tegra194 Vidya Sagar
2019-07-01 12:40 ` Vidya Sagar
2019-07-01 12:40 ` Vidya Sagar
2019-07-01 12:40 ` [PATCH V12 10/12] dt-bindings: PHY: P2U: Add Tegra194 P2U block Vidya Sagar
2019-07-01 12:40 ` Vidya Sagar
2019-07-01 12:40 ` Vidya Sagar
2019-07-01 12:40 ` [PATCH V12 11/12] phy: tegra: Add PCIe PIPE2UPHY support Vidya Sagar
2019-07-01 12:40 ` Vidya Sagar
2019-07-01 12:40 ` Vidya Sagar
2019-07-01 12:40 ` [PATCH V12 12/12] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
2019-07-01 12:40 ` Vidya Sagar
2019-07-01 12:40 ` Vidya Sagar
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190701124010.7484-2-vidyas@nvidia.com \
--to=vidyas@nvidia.com \
--cc=bhelgaas@google.com \
--cc=catalin.marinas@arm.com \
--cc=devicetree@vger.kernel.org \
--cc=digetx@gmail.com \
--cc=gustavo.pimentel@synopsys.com \
--cc=jingoohan1@gmail.com \
--cc=jonathanh@nvidia.com \
--cc=kishon@ti.com \
--cc=kthota@nvidia.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=mark.rutland@arm.com \
--cc=mmaddireddy@nvidia.com \
--cc=mperttunen@nvidia.com \
--cc=robh+dt@kernel.org \
--cc=sagar.tv@gmail.com \
--cc=thierry.reding@gmail.com \
--cc=will.deacon@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.