All of lore.kernel.org
 help / color / mirror / Atom feed
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	bhelgaas@google.com, robh+dt@kernel.org, mark.rutland@arm.com,
	l.subrahmanya@mobiveil.co.in, shawnguo@kernel.org,
	leoyang.li@nxp.com, lorenzo.pieralisi@arm.com,
	catalin.marinas@arm.com, will.deacon@arm.com
Cc: Mingkai.Hu@nxp.com, Minghuan.Lian@nxp.com, Xiaowei.Bao@nxp.com,
	Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Subject: [PATCHv6 12/28] dt-bindings: PCI: mobiveil: Change gpio_slave and apb_csr to optional
Date: Fri,  5 Jul 2019 17:56:40 +0800	[thread overview]
Message-ID: <20190705095656.19191-13-Zhiqiang.Hou@nxp.com> (raw)
In-Reply-To: <20190705095656.19191-1-Zhiqiang.Hou@nxp.com>

Change the "gpio_slave" and "apb_csr" to optional, the "gpio_slave"
is not used in current code, and "apb_csr" is not used by some platforms.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Acked-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
---
V6:
 - Rebased the patch, no functional change.

 .../devicetree/bindings/pci/mobiveil-pcie.txt      |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt b/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt
index a618d47..6415699 100644
--- a/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt
@@ -10,8 +10,10 @@ Required properties:
 	interrupt source. The value must be 1.
 - compatible: Should contain "mbvl,gpex40-pcie"
 - reg: Should contain PCIe registers location and length
+	Mandatory:
 	"config_axi_slave": PCIe controller registers
 	"csr_axi_slave"	  : Bridge config registers
+	Optional:
 	"gpio_slave"	  : GPIO registers to control slot power
 	"apb_csr"	  : MSI registers
 
-- 
1.7.1


WARNING: multiple messages have this Message-ID (diff)
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	bhelgaas@google.com, robh+dt@kernel.org, mark.rutland@arm.com,
	l.subrahmanya@mobiveil.co.in, shawnguo@kernel.org,
	leoyang.li@nxp.com, lorenzo.pieralisi@arm.com,
	catalin.marinas@arm.com, will.deacon@arm.com
Cc: Minghuan.Lian@nxp.com, Hou Zhiqiang <Zhiqiang.Hou@nxp.com>,
	Xiaowei.Bao@nxp.com, Mingkai.Hu@nxp.com
Subject: [PATCHv6 12/28] dt-bindings: PCI: mobiveil: Change gpio_slave and apb_csr to optional
Date: Fri,  5 Jul 2019 17:56:40 +0800	[thread overview]
Message-ID: <20190705095656.19191-13-Zhiqiang.Hou@nxp.com> (raw)
In-Reply-To: <20190705095656.19191-1-Zhiqiang.Hou@nxp.com>

Change the "gpio_slave" and "apb_csr" to optional, the "gpio_slave"
is not used in current code, and "apb_csr" is not used by some platforms.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Acked-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
---
V6:
 - Rebased the patch, no functional change.

 .../devicetree/bindings/pci/mobiveil-pcie.txt      |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt b/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt
index a618d47..6415699 100644
--- a/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt
@@ -10,8 +10,10 @@ Required properties:
 	interrupt source. The value must be 1.
 - compatible: Should contain "mbvl,gpex40-pcie"
 - reg: Should contain PCIe registers location and length
+	Mandatory:
 	"config_axi_slave": PCIe controller registers
 	"csr_axi_slave"	  : Bridge config registers
+	Optional:
 	"gpio_slave"	  : GPIO registers to control slot power
 	"apb_csr"	  : MSI registers
 
-- 
1.7.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2019-07-05 10:08 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-05  9:56 [PATCHv6 00/28] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Hou Zhiqiang
2019-07-05  9:56 ` Hou Zhiqiang
2019-07-05  9:56 ` [PATCHv6 01/28] PCI: mobiveil: Unify register accessors Hou Zhiqiang
2019-07-05  9:56   ` Hou Zhiqiang
2019-07-05  9:56 ` [PATCHv6 02/28] PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI Hou Zhiqiang
2019-07-05  9:56   ` Hou Zhiqiang
2019-07-05  9:56 ` [PATCHv6 03/28] PCI: mobiveil: Fix PCI base address in MEM/IO outbound windows Hou Zhiqiang
2019-07-05  9:56   ` Hou Zhiqiang
2019-07-05  9:56 ` [PATCHv6 04/28] PCI: mobiveil: Update the resource list traversal function Hou Zhiqiang
2019-07-05  9:56   ` Hou Zhiqiang
2019-07-05  9:56 ` [PATCHv6 05/28] PCI: mobiveil: Use WIN_NUM_0 explicitly for CFG outbound window Hou Zhiqiang
2019-07-05  9:56   ` Hou Zhiqiang
2019-07-05  9:56 ` [PATCHv6 06/28] PCI: mobiveil: Use the 1st inbound window for MEM inbound transactions Hou Zhiqiang
2019-07-05  9:56   ` Hou Zhiqiang
2019-07-05  9:56 ` [PATCHv6 07/28] PCI: mobiveil: Fix the Class Code field Hou Zhiqiang
2019-07-05  9:56   ` Hou Zhiqiang
2019-07-05  9:56 ` [PATCHv6 08/28] PCI: mobiveil: Move the link up waiting out of mobiveil_host_init() Hou Zhiqiang
2019-07-05  9:56   ` Hou Zhiqiang
2019-07-05  9:56 ` [PATCHv6 09/28] PCI: mobiveil: Move IRQ chained handler setup out of DT parse Hou Zhiqiang
2019-07-05  9:56   ` Hou Zhiqiang
2019-07-05  9:56 ` [PATCHv6 10/28] PCI: mobiveil: Initialize Primary/Secondary/Subordinate bus numbers Hou Zhiqiang
2019-07-05  9:56   ` Hou Zhiqiang
2019-07-05  9:56 ` [PATCHv6 11/28] PCI: mobiveil: Fix devfn check in mobiveil_pcie_valid_device() Hou Zhiqiang
2019-07-05  9:56   ` Hou Zhiqiang
2019-07-05  9:56 ` Hou Zhiqiang [this message]
2019-07-05  9:56   ` [PATCHv6 12/28] dt-bindings: PCI: mobiveil: Change gpio_slave and apb_csr to optional Hou Zhiqiang
2019-07-05  9:56 ` [PATCHv6 13/28] PCI: mobiveil: Reformat the code for readability Hou Zhiqiang
2019-07-05  9:56   ` Hou Zhiqiang
2019-07-05  9:56 ` [PATCHv6 14/28] PCI: mobiveil: Make the register updating more readable Hou Zhiqiang
2019-07-05  9:56   ` Hou Zhiqiang
2019-07-05  9:56 ` [PATCHv6 15/28] PCI: mobiveil: Revise the MEM/IO outbound window initialization Hou Zhiqiang
2019-07-05  9:56   ` Hou Zhiqiang
2019-07-05  9:56 ` [PATCHv6 16/28] PCI: mobiveil: Fix the returned error number Hou Zhiqiang
2019-07-05  9:56   ` Hou Zhiqiang
2019-07-05  9:56 ` [PATCHv6 17/28] PCI: mobiveil: Remove an unnecessary return value check Hou Zhiqiang
2019-07-05  9:56   ` Hou Zhiqiang
2019-07-05  9:56 ` [PATCHv6 18/28] PCI: mobiveil: Remove redundant var definitions and register read operations Hou Zhiqiang
2019-07-05  9:56   ` Hou Zhiqiang
2019-07-05  9:56   ` Hou Zhiqiang
2019-07-05  9:56 ` [PATCHv6 19/28] PCI: mobiveil: Fix the valid check for inbound and outbound window Hou Zhiqiang
2019-07-05  9:56   ` Hou Zhiqiang
2019-07-05  9:56 ` [PATCHv6 20/28] PCI: mobiveil: Add the statistic of initialized inbound windows Hou Zhiqiang
2019-07-05  9:56   ` Hou Zhiqiang
2019-07-05  9:56 ` [PATCHv6 21/28] PCI: mobiveil: Clear the target fields before updating the register Hou Zhiqiang
2019-07-05  9:56   ` Hou Zhiqiang
2019-07-05  9:56 ` [PATCHv6 22/28] PCI: mobiveil: Mask out the lower 10-bit hardcode window size Hou Zhiqiang
2019-07-05  9:56   ` Hou Zhiqiang
2019-07-05  9:56 ` [PATCHv6 23/28] PCI: mobiveil: Add upper 32-bit CPU base address setup in outbound window Hou Zhiqiang
2019-07-05  9:56   ` Hou Zhiqiang
2019-07-05  9:56 ` [PATCHv6 24/28] PCI: mobiveil: Add upper 32-bit PCI base address setup in inbound window Hou Zhiqiang
2019-07-05  9:56   ` Hou Zhiqiang
2019-07-05  9:56 ` [PATCHv6 25/28] PCI: mobiveil: Fix the CPU " Hou Zhiqiang
2019-07-05  9:56   ` Hou Zhiqiang
2019-07-05  9:56 ` [PATCHv6 26/28] PCI: mobiveil: Move PCIe PIO enablement out of inbound window routine Hou Zhiqiang
2019-07-05  9:56   ` Hou Zhiqiang
2019-07-05  9:56 ` [PATCHv6 27/28] PCI: mobiveil: Fix infinite-loop in the INTx process Hou Zhiqiang
2019-07-05  9:56   ` Hou Zhiqiang
2019-07-05  9:56 ` [PATCHv6 28/28] PCI: mobiveil: Fix the potential INTx missing problem Hou Zhiqiang
2019-07-05  9:56   ` Hou Zhiqiang
2019-07-08 11:35 ` [PATCHv6 00/28] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Lorenzo Pieralisi
2019-07-08 11:35   ` Lorenzo Pieralisi
2019-07-10 10:59   ` Z.q. Hou
2019-07-10 10:59     ` Z.q. Hou
2019-07-10 10:59     ` Z.q. Hou

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20190705095656.19191-13-Zhiqiang.Hou@nxp.com \
    --to=zhiqiang.hou@nxp.com \
    --cc=Minghuan.Lian@nxp.com \
    --cc=Mingkai.Hu@nxp.com \
    --cc=Xiaowei.Bao@nxp.com \
    --cc=bhelgaas@google.com \
    --cc=catalin.marinas@arm.com \
    --cc=devicetree@vger.kernel.org \
    --cc=l.subrahmanya@mobiveil.co.in \
    --cc=leoyang.li@nxp.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=lorenzo.pieralisi@arm.com \
    --cc=mark.rutland@arm.com \
    --cc=robh+dt@kernel.org \
    --cc=shawnguo@kernel.org \
    --cc=will.deacon@arm.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.