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From: Anshuman Gupta <anshuman.gupta@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com
Subject: [PATCH v2 01/10] drm/i915/tgl:Added DC3CO required register and bits.
Date: Wed, 17 Jul 2019 15:57:56 +0530	[thread overview]
Message-ID: <20190717102804.27202-2-anshuman.gupta@intel.com> (raw)
In-Reply-To: <20190717102804.27202-1-anshuman.gupta@intel.com>

This patch adds following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
2. Transcoder EXITLINE register and its bit fields and mask.

v2: Commit log typo fixing.

Cc: jani.nikula@intel.com
Cc: imre.deak@intel.com
Cc: animesh.manna@intel.com
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a244e8158aee..df36d84a7a8d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4185,6 +4185,7 @@ enum {
 #define _VTOTAL_A	0x6000c
 #define _VBLANK_A	0x60010
 #define _VSYNC_A	0x60014
+#define _EXITLINE_A	0x60018
 #define _PIPEASRC	0x6001c
 #define _BCLRPAT_A	0x60020
 #define _VSYNCSHIFT_A	0x60028
@@ -4231,11 +4232,16 @@ enum {
 #define VTOTAL(trans)		_MMIO_TRANS2(trans, _VTOTAL_A)
 #define VBLANK(trans)		_MMIO_TRANS2(trans, _VBLANK_A)
 #define VSYNC(trans)		_MMIO_TRANS2(trans, _VSYNC_A)
+#define EXITLINE(trans)		_MMIO_TRANS2(trans, _EXITLINE_A)
 #define BCLRPAT(trans)		_MMIO_TRANS2(trans, _BCLRPAT_A)
 #define VSYNCSHIFT(trans)	_MMIO_TRANS2(trans, _VSYNCSHIFT_A)
 #define PIPESRC(trans)		_MMIO_TRANS2(trans, _PIPEASRC)
 #define PIPE_MULT(trans)	_MMIO_TRANS2(trans, _PIPE_MULT_A)
 
+#define  EXITLINE_ENABLE	(1 << 31)
+#define  EXITLINE_MASK		(0x1fff)
+#define  EXITLINE_SHIFT		0
+
 /* HSW+ eDP PSR registers */
 #define HSW_EDP_PSR_BASE	0x64800
 #define BDW_EDP_PSR_BASE	0x6f800
@@ -9988,6 +9994,8 @@ enum skl_power_gate {
 /* GEN9 DC */
 #define DC_STATE_EN			_MMIO(0x45504)
 #define  DC_STATE_DISABLE		0
+#define  DC_STATE_EN_DC3CO		(1 << 30)
+#define  DC_STATE_DC3CO_STATUS		(1 << 29)
 #define  DC_STATE_EN_UPTO_DC5		(1 << 0)
 #define  DC_STATE_EN_DC9		(1 << 3)
 #define  DC_STATE_EN_UPTO_DC6		(2 << 0)
-- 
2.21.0

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  reply	other threads:[~2019-07-17 10:32 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-17 10:27 [PATCH v2 00/10] DC3CO Support for TGL Anshuman Gupta
2019-07-17 10:27 ` Anshuman Gupta [this message]
2019-07-17 10:27 ` [PATCH v2 02/10] i915:Added DC3CO mask to allowed_dc_mask and gen9_dc_mask Anshuman Gupta
2019-07-29 12:41   ` Jani Nikula
2019-07-17 10:27 ` [PATCH v2 03/10] i915:Added DC3CO power well Anshuman Gupta
2019-07-17 10:27 ` [PATCH v2 04/10] drm/i915/tgl:Added mutual exclusive handling for DC3CO and DC5/6 Anshuman Gupta
2019-07-17 10:28 ` [PATCH v2 05/10] drm/i915/tgl:Added helper function to prefer dc3co over dc5 Anshuman Gupta
2019-07-17 10:28 ` [PATCH v2 06/10] drm/i915/tgl:Added VIDEO power domain Anshuman Gupta
2019-07-17 10:28 ` [PATCH v2 07/10] drm/i915/tgl:DC3CO PSR2 helper Anshuman Gupta
2019-07-17 10:28 ` [PATCH v2 08/10] drm/i915/tgl:switch between dc3co and dc5 based on display idleness Anshuman Gupta
2019-07-17 10:28 ` [PATCH v2 09/10] drm/i915/tgl:Added DC3CO counter in i915_dmc_info Anshuman Gupta
  -- strict thread matches above, loose matches on Subject: below --
2019-07-17 14:09 [PATCH v2 00/10] DC3CO Support for TGL Anshuman Gupta
2019-07-17 14:09 ` [PATCH v2 01/10] drm/i915/tgl:Added DC3CO required register and bits Anshuman Gupta
2019-07-12 16:29 [PATCH v2 00/10] DC3CO Support for TGL Anshuman Gupta
2019-07-12 16:29 ` [PATCH v2 01/10] drm/i915/tgl:Added DC3CO required register and bits Anshuman Gupta

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