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From: Linus Walleij <linus.walleij@linaro.org>
To: Daniel Tang <dt.tangr@gmail.com>, Fabian Vogt <fabian@ritter-vogt.de>
Cc: Linus Walleij <linus.walleij@linaro.org>,
	dri-devel@lists.freedesktop.org,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH 0/3] RFT: PL111 DRM conversion of nspire
Date: Tue, 23 Jul 2019 15:37:52 +0200	[thread overview]
Message-ID: <20190723133755.22677-1-linus.walleij@linaro.org> (raw)

So this is a cold-coded attempt to move the TI nspire over to
using DRM. It is more or less the last user of the old fbdev
driver so it is a noble cause and interesting usecase.

This can be applied on top of a vanilla Torvalds v5.3-rc1
kernel out since sunday.

I do not expect these patches to "just work", I expect them to
need some hacking, so someone who is actually working on the
hardware will need to step in and fix it up.

It does outline the overall idea of how to do this.

I found no defconfig for nspire in the kernel so I used
ARMv4t multi.

Configuring the driver for nspire:

- Disable CONFIG_FB_ARMCLCD
- Enable CONFIG_DRM_PL111, CONFIG_DRM_PANEL_SIMPLE

Hacker notes for nspire:

- I don't know which PrimeCell ID this hardware has, I hope
  the amba_id mask in drivers/gpu/drm/pl111/pl111_drv.c for
  PL111 and PL110 will match it. Please confirm that you get
  a clean probe call, else report what ID this has.

- The 24bit RGB frame buffer may be a bit much for the PL111
  in the TI nspire to handle. Try editing the .fb_bpp in
  drivers/gpu/drm/pl111/pl111_drv.c down to 16 if this is
  the PL111 variant. If it is the PL110 variant, we will get
  16 buts framebuffer anyway.

- I have hard-coded the panels to 1MHz, based on the fact
  that the AHB clock into the CLCD appears to be 48 MHz
  and the hard-coded TIM2 value for the classic means
  "divide by 48" and this seems to want the clock freq
  divided down to 1MHz. Verify this by adding prints
  inside drivers/gpu/drm/pl111/pl111_display.c in the
  function pl111_clk_div_set_rate() to verify that the
  divider gets set to 48 in TIM2_PCD_HI and
  TIM2_PCD_LO. TIM2_PCD_LO bits 0..4 = 10000 and
  TIM2_PCD_HI bits 27..31 = 00001 in that register.

Please test and fix, if you can.

Linus Walleij (3):
  RFT: drm/pl111: Support grayscale
  RTF: drm/panel: simple: Add TI nspire panels
  RFT: ARM: nspire: Move CLCD set-up to device tree

 arch/arm/boot/dts/nspire-classic.dtsi |  19 ++++-
 arch/arm/boot/dts/nspire-cx.dts       |  18 +++-
 arch/arm/boot/dts/nspire.dtsi         |  10 ++-
 arch/arm/mach-nspire/Makefile         |   1 -
 arch/arm/mach-nspire/clcd.c           | 114 --------------------------
 arch/arm/mach-nspire/clcd.h           |  10 ---
 arch/arm/mach-nspire/nspire.c         |  25 ------
 drivers/gpu/drm/panel/panel-simple.c  |  63 ++++++++++++++
 drivers/gpu/drm/pl111/pl111_display.c |  28 ++++++-
 include/linux/amba/clcd-regs.h        |   1 +
 10 files changed, 133 insertions(+), 156 deletions(-)
 delete mode 100644 arch/arm/mach-nspire/clcd.c
 delete mode 100644 arch/arm/mach-nspire/clcd.h

-- 
2.21.0


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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: Linus Walleij <linus.walleij@linaro.org>
To: Daniel Tang <dt.tangr@gmail.com>, Fabian Vogt <fabian@ritter-vogt.de>
Cc: dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH 0/3] RFT: PL111 DRM conversion of nspire
Date: Tue, 23 Jul 2019 15:37:52 +0200	[thread overview]
Message-ID: <20190723133755.22677-1-linus.walleij@linaro.org> (raw)

So this is a cold-coded attempt to move the TI nspire over to
using DRM. It is more or less the last user of the old fbdev
driver so it is a noble cause and interesting usecase.

This can be applied on top of a vanilla Torvalds v5.3-rc1
kernel out since sunday.

I do not expect these patches to "just work", I expect them to
need some hacking, so someone who is actually working on the
hardware will need to step in and fix it up.

It does outline the overall idea of how to do this.

I found no defconfig for nspire in the kernel so I used
ARMv4t multi.

Configuring the driver for nspire:

- Disable CONFIG_FB_ARMCLCD
- Enable CONFIG_DRM_PL111, CONFIG_DRM_PANEL_SIMPLE

Hacker notes for nspire:

- I don't know which PrimeCell ID this hardware has, I hope
  the amba_id mask in drivers/gpu/drm/pl111/pl111_drv.c for
  PL111 and PL110 will match it. Please confirm that you get
  a clean probe call, else report what ID this has.

- The 24bit RGB frame buffer may be a bit much for the PL111
  in the TI nspire to handle. Try editing the .fb_bpp in
  drivers/gpu/drm/pl111/pl111_drv.c down to 16 if this is
  the PL111 variant. If it is the PL110 variant, we will get
  16 buts framebuffer anyway.

- I have hard-coded the panels to 1MHz, based on the fact
  that the AHB clock into the CLCD appears to be 48 MHz
  and the hard-coded TIM2 value for the classic means
  "divide by 48" and this seems to want the clock freq
  divided down to 1MHz. Verify this by adding prints
  inside drivers/gpu/drm/pl111/pl111_display.c in the
  function pl111_clk_div_set_rate() to verify that the
  divider gets set to 48 in TIM2_PCD_HI and
  TIM2_PCD_LO. TIM2_PCD_LO bits 0..4 = 10000 and
  TIM2_PCD_HI bits 27..31 = 00001 in that register.

Please test and fix, if you can.

Linus Walleij (3):
  RFT: drm/pl111: Support grayscale
  RTF: drm/panel: simple: Add TI nspire panels
  RFT: ARM: nspire: Move CLCD set-up to device tree

 arch/arm/boot/dts/nspire-classic.dtsi |  19 ++++-
 arch/arm/boot/dts/nspire-cx.dts       |  18 +++-
 arch/arm/boot/dts/nspire.dtsi         |  10 ++-
 arch/arm/mach-nspire/Makefile         |   1 -
 arch/arm/mach-nspire/clcd.c           | 114 --------------------------
 arch/arm/mach-nspire/clcd.h           |  10 ---
 arch/arm/mach-nspire/nspire.c         |  25 ------
 drivers/gpu/drm/panel/panel-simple.c  |  63 ++++++++++++++
 drivers/gpu/drm/pl111/pl111_display.c |  28 ++++++-
 include/linux/amba/clcd-regs.h        |   1 +
 10 files changed, 133 insertions(+), 156 deletions(-)
 delete mode 100644 arch/arm/mach-nspire/clcd.c
 delete mode 100644 arch/arm/mach-nspire/clcd.h

-- 
2.21.0

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

             reply	other threads:[~2019-07-23 13:38 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-23 13:37 Linus Walleij [this message]
2019-07-23 13:37 ` [PATCH 0/3] RFT: PL111 DRM conversion of nspire Linus Walleij
2019-07-23 13:37 ` [PATCH 1/3] RFT: drm/pl111: Support grayscale Linus Walleij
2019-07-23 13:37   ` Linus Walleij
2019-07-23 15:19   ` Fabian Vogt
2019-07-23 15:19     ` Fabian Vogt
2019-07-24 12:33     ` Linus Walleij
2019-07-24 12:33       ` Linus Walleij
2019-07-25 19:26       ` Fabian Vogt
2019-07-25 19:26         ` Fabian Vogt
2019-08-03  9:51         ` Linus Walleij
2019-08-03  9:51           ` Linus Walleij
2019-08-04 20:13           ` Fabian Vogt
2019-08-04 20:13             ` Fabian Vogt
2019-07-23 16:22   ` [1/3] " David Lechner
2019-07-23 16:22     ` David Lechner
2019-07-23 17:25   ` [PATCH 1/3] " Adam Jackson
2019-07-23 17:25     ` Adam Jackson
2019-07-23 21:06     ` Daniel Vetter
2019-07-23 21:06       ` Daniel Vetter
2019-07-24 12:52       ` Linus Walleij
2019-07-24 12:52         ` Linus Walleij
2019-07-24 14:06         ` Daniel Vetter
2019-07-24 14:06           ` Daniel Vetter
2019-07-23 13:37 ` [PATCH 2/3] RTF: drm/panel: simple: Add TI nspire panels Linus Walleij
2019-07-23 13:37   ` Linus Walleij
2019-07-23 17:54   ` Sam Ravnborg
2019-07-23 17:54     ` Sam Ravnborg
2019-07-24 13:58     ` Linus Walleij
2019-07-24 13:58       ` Linus Walleij
2019-07-24 18:53       ` Sam Ravnborg
2019-07-24 18:53         ` Sam Ravnborg
2019-07-23 13:37 ` [PATCH 3/3] RFT: ARM: nspire: Move CLCD set-up to device tree Linus Walleij
2019-07-23 13:37   ` Linus Walleij
2019-07-23 18:10 ` [PATCH 0/3] RFT: PL111 DRM conversion of nspire Sam Ravnborg
2019-07-23 18:10   ` Sam Ravnborg
2019-07-24 12:28   ` Linus Walleij
2019-07-24 12:28     ` Linus Walleij
2019-07-24 12:47     ` Pawel Moll
2019-07-24 12:47       ` Pawel Moll
2019-07-24 12:53       ` Linus Walleij
2019-07-24 12:53         ` Linus Walleij

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