From: "Moger, Babu" <Babu.Moger@amd.com>
To: "ehabkost@redhat.com" <ehabkost@redhat.com>,
"marcel.apfelbaum@gmail.com" <marcel.apfelbaum@gmail.com>,
"mst@redhat.com" <mst@redhat.com>,
"pbonzini@redhat.com" <pbonzini@redhat.com>,
"rth@twiddle.net" <rth@twiddle.net>,
"imammedo@redhat.com" <imammedo@redhat.com>
Cc: "Moger, Babu" <Babu.Moger@amd.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Subject: [Qemu-devel] [RFC PATCH 0/5] APIC ID fixes for AMD EPYC CPU models
Date: Wed, 31 Jul 2019 23:20:45 +0000 [thread overview]
Message-ID: <20190731232032.51786-1-babu.moger@amd.com> (raw)
These series fixes the problems encoding APIC ID for AMD EPYC cpu models.
https://bugzilla.redhat.com/show_bug.cgi?id=1728166
This is the first pass to give an idea of the changes required to address
the issue. Please feel free to comment.
Currently, apic id is decoded based on sockets/dies/cores/threads. This appears
to work for most standard configurations for AMD and other vendors. But this
decoding does not follow AMD's APIC ID enumeration. In some cases this
causes CPU topology inconstancy. While booting guest Kernel is trying to
validate topology. It finds the topology not aligning to EPYC models.
To fix the problem we need to build the topology as per the
Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1
Processors. It is available at https://www.amd.com/en/support/tech-docs
Here is the text from the PPR.
2.1.10.2.1.3
ApicId Enumeration Requirements
Operating systems are expected to use
Core::X86::Cpuid::SizeId[ApicIdCoreIdSize], the number of least
significant bits in the Initial APIC ID that indicate core ID within a
processor, in constructing per-core CPUID
masks. Core::X86::Cpuid::SizeId[ApicIdCoreIdSize] determines the maximum number
of cores (MNC) that the
processor could theoretically support, not the actual number of cores that are
actually implemented or enabled on
the processor, as indicated by Core::X86::Cpuid::SizeId[NC].
Each Core::X86::Apic::ApicId[ApicId] register is preset as follows:
• ApicId[6] = Socket ID.
• ApicId[5:4] = Node ID.
• ApicId[3] = Logical CCX L3 complex ID
• ApicId[2:0]= (SMT) ? {LogicalCoreID[1:0],ThreadId} :
{1'b0,LogicalCoreID[1:0]}.
"""
Babu Moger (5):
hw/boards: Add sockets in CpuTopology structure
hw/i386: Add AMD EPYC topology encoding
i386: Use topology functions from topology.h
hw/i386: Generate apicid based on cpu_type
i386: Fix pkg_id offset EPYC
hw/core/machine.c | 1 +
hw/i386/pc.c | 82 ++++++++++++++++---
include/hw/boards.h | 2 +
include/hw/i386/topology.h | 140 ++++++++++++++++++++++++++++++++
target/i386/cpu.c | 160 +++++++++----------------------------
vl.c | 1 +
6 files changed, 251 insertions(+), 135 deletions(-)
--
2.20.1
next reply other threads:[~2019-07-31 23:22 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-31 23:20 Moger, Babu [this message]
2019-07-31 23:20 ` [Qemu-devel] [RFC PATCH 1/5] hw/boards: Add sockets in CpuTopology structure Moger, Babu
2019-07-31 23:20 ` [Qemu-devel] [RFC PATCH 2/5] hw/i386: Add AMD EPYC topology encoding Moger, Babu
2019-07-31 23:20 ` [Qemu-devel] [RFC PATCH 3/5] i386: Use topology functions from topology.h Moger, Babu
2019-07-31 23:20 ` [Qemu-devel] [RFC PATCH 4/5] hw/i386: Generate apicid based on cpu_type Moger, Babu
2019-08-01 19:28 ` Eduardo Habkost
2019-08-01 19:37 ` Moger, Babu
2019-07-31 23:20 ` [Qemu-devel] [RFC PATCH 5/5] i386: Fix pkg_id offset EPYC Moger, Babu
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