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From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [PATCH 2/2] drm/i915/tgl: Fix the read of the DDI that transcoder is attached to
Date: Thu,  1 Aug 2019 16:28:12 -0700	[thread overview]
Message-ID: <20190801232812.28375-2-jose.souza@intel.com> (raw)
In-Reply-To: <20190801232812.28375-1-jose.souza@intel.com>

On TGL this register do not map directly to port, it was already
handled when setting it(TGL_TRANS_DDI_SELECT_PORT()) but not when
reading it.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9e4ee29fd0fc..b9526aa402f9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10353,11 +10353,17 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
 
 	tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
 
-	if (INTEL_GEN(dev_priv) >= 12)
+	if (INTEL_GEN(dev_priv) >= 12) {
 		port = (tmp & TGL_TRANS_DDI_PORT_MASK) >>
 			TGL_TRANS_DDI_PORT_SHIFT;
-	else
+		/*
+		 * Register values: none = 0, DDIA = 1... while PORT_A = 0...
+		 * so subtract one
+		 */
+		port--;
+	} else {
 		port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
+	}
 
 	if (INTEL_GEN(dev_priv) >= 11)
 		icelake_get_ddi_pll(dev_priv, port, pipe_config);
-- 
2.22.0

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  reply	other threads:[~2019-08-01 23:28 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-01 23:28 [PATCH 1/2] drm/i915: Get transcoder power domain before reading its register José Roberto de Souza
2019-08-01 23:28 ` José Roberto de Souza [this message]
2019-08-02  0:50   ` [PATCH 2/2] drm/i915/tgl: Fix the read of the DDI that transcoder is attached to Lucas De Marchi
2019-08-02  1:07     ` Souza, Jose
2019-08-01 23:54 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Get transcoder power domain before reading its register Patchwork
2019-08-02  0:15 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-02  0:41 ` [PATCH 1/2] " Lucas De Marchi
2019-08-02  1:08   ` Souza, Jose
2019-08-02 22:59 ` ✓ Fi.CI.IGT: success for series starting with [1/2] " Patchwork

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