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From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org, Yan Markman <ymarkman@marvell.com>,
	Antoine Tenart <antoine.tenart@bootlin.com>,
	Grzegorz Jaszczyk <jaz@semihalf.com>,
	Gregory Clement <gregory.clement@bootlin.com>,
	Maxime Chevallier <maxime.chevallier@bootlin.com>,
	Nadav Haklai <nadavh@marvell.com>,
	Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	Miquel Raynal <miquel.raynal@bootlin.com>,
	Stefan Chulski <stefanc@marvell.com>,
	Marcin Wojtas <mw@semihalf.com>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH 17/20] arm64: dts: marvell: Add support for Marvell CN9130 SoC support
Date: Tue,  6 Aug 2019 16:54:57 +0200	[thread overview]
Message-ID: <20190806145500.24109-18-miquel.raynal@bootlin.com> (raw)
In-Reply-To: <20190806145500.24109-1-miquel.raynal@bootlin.com>

A CN9130 SoC has one AP807 and one internal CP115.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
 arch/arm64/boot/dts/marvell/cn9130.dtsi | 37 +++++++++++++++++++++++++
 1 file changed, 37 insertions(+)
 create mode 100644 arch/arm64/boot/dts/marvell/cn9130.dtsi

diff --git a/arch/arm64/boot/dts/marvell/cn9130.dtsi b/arch/arm64/boot/dts/marvell/cn9130.dtsi
new file mode 100644
index 000000000000..a2b7e5ec979d
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9130.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * Device tree for the CN9130 SoC.
+ */
+
+#include "armada-ap807-quad.dtsi"
+
+/ {
+	model = "Marvell Armada CN9130 SoC";
+	compatible = "marvell,cn9130", "marvell,armada-ap807-quad",
+		     "marvell,armada-ap807";
+};
+
+/*
+ * Instantiate the internal CP115
+ */
+
+#define CP11X_NAME		cp0
+#define CP11X_BASE		f2000000
+#define CP11X_PCIEx_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \
+						    0xe0000000 + ((iface - 1) * 0x1000000))
+#define CP11X_PCIEx_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000)
+#define CP11X_PCIE0_BASE	f2600000
+#define CP11X_PCIE1_BASE	f2620000
+#define CP11X_PCIE2_BASE	f2640000
+
+#include "armada-cp115.dtsi"
+
+#undef CP11X_NAME
+#undef CP11X_BASE
+#undef CP11X_PCIEx_MEM_BASE
+#undef CP11X_PCIEx_MEM_SIZE
+#undef CP11X_PCIE0_BASE
+#undef CP11X_PCIE1_BASE
+#undef CP11X_PCIE2_BASE
-- 
2.20.1

WARNING: multiple messages have this Message-ID (diff)
From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org, Yan Markman <ymarkman@marvell.com>,
	Antoine Tenart <antoine.tenart@bootlin.com>,
	Grzegorz Jaszczyk <jaz@semihalf.com>,
	Gregory Clement <gregory.clement@bootlin.com>,
	Maxime Chevallier <maxime.chevallier@bootlin.com>,
	Nadav Haklai <nadavh@marvell.com>,
	Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	Miquel Raynal <miquel.raynal@bootlin.com>,
	Stefan Chulski <stefanc@marvell.com>,
	Marcin Wojtas <mw@semihalf.com>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH 17/20] arm64: dts: marvell: Add support for Marvell CN9130 SoC support
Date: Tue,  6 Aug 2019 16:54:57 +0200	[thread overview]
Message-ID: <20190806145500.24109-18-miquel.raynal@bootlin.com> (raw)
In-Reply-To: <20190806145500.24109-1-miquel.raynal@bootlin.com>

A CN9130 SoC has one AP807 and one internal CP115.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
 arch/arm64/boot/dts/marvell/cn9130.dtsi | 37 +++++++++++++++++++++++++
 1 file changed, 37 insertions(+)
 create mode 100644 arch/arm64/boot/dts/marvell/cn9130.dtsi

diff --git a/arch/arm64/boot/dts/marvell/cn9130.dtsi b/arch/arm64/boot/dts/marvell/cn9130.dtsi
new file mode 100644
index 000000000000..a2b7e5ec979d
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9130.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * Device tree for the CN9130 SoC.
+ */
+
+#include "armada-ap807-quad.dtsi"
+
+/ {
+	model = "Marvell Armada CN9130 SoC";
+	compatible = "marvell,cn9130", "marvell,armada-ap807-quad",
+		     "marvell,armada-ap807";
+};
+
+/*
+ * Instantiate the internal CP115
+ */
+
+#define CP11X_NAME		cp0
+#define CP11X_BASE		f2000000
+#define CP11X_PCIEx_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \
+						    0xe0000000 + ((iface - 1) * 0x1000000))
+#define CP11X_PCIEx_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000)
+#define CP11X_PCIE0_BASE	f2600000
+#define CP11X_PCIE1_BASE	f2620000
+#define CP11X_PCIE2_BASE	f2640000
+
+#include "armada-cp115.dtsi"
+
+#undef CP11X_NAME
+#undef CP11X_BASE
+#undef CP11X_PCIEx_MEM_BASE
+#undef CP11X_PCIEx_MEM_SIZE
+#undef CP11X_PCIE0_BASE
+#undef CP11X_PCIE1_BASE
+#undef CP11X_PCIE2_BASE
-- 
2.20.1


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  parent reply	other threads:[~2019-08-06 14:54 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-06 14:54 [PATCH 00/20] Add new Marvell CN9130 SoC support Miquel Raynal
2019-08-06 14:54 ` [PATCH 01/20] arm64: dts: marvell: Enumerate the first AP806 syscon Miquel Raynal
2019-08-06 14:54   ` Miquel Raynal
2019-08-06 14:54 ` [PATCH 02/20] arm64: dts: marvell: Add AP806-dual missing CPU clocks Miquel Raynal
2019-08-06 14:54   ` Miquel Raynal
2019-08-06 14:54 ` [PATCH 03/20] dt-bindings: ap80x: replace AP806 with AP80x Miquel Raynal
2019-08-06 14:54   ` Miquel Raynal
2019-08-21 19:32   ` Rob Herring
2019-08-21 19:32     ` Rob Herring
2019-08-06 14:54 ` [PATCH 04/20] MAINTAINERS: Add new Marvell CN9130-based files to track Miquel Raynal
2019-08-06 14:54   ` Miquel Raynal
2019-08-06 14:54 ` [PATCH 05/20] arm64: dts: marvell: Prepare the introduction of AP807 based SoCs Miquel Raynal
2019-08-06 14:54   ` Miquel Raynal
2019-08-27 15:20   ` Gregory CLEMENT
2019-08-27 15:20     ` Gregory CLEMENT
2019-08-06 14:54 ` [PATCH 06/20] arm64: dts: marvell: Move clocks to AP806 specific file Miquel Raynal
2019-08-06 14:54   ` Miquel Raynal
2019-08-06 14:54 ` [PATCH 07/20] arm64: dts: marvell: Add support for AP807/AP807-quad Miquel Raynal
2019-08-06 14:54   ` Miquel Raynal
2019-08-06 14:54 ` [PATCH 08/20] arm64: dts: marvell: Add AP806-dual cache description Miquel Raynal
2019-08-06 14:54   ` Miquel Raynal
2019-08-06 14:54 ` [PATCH 09/20] arm64: dts: marvell: Add AP806-quad " Miquel Raynal
2019-08-06 14:54   ` Miquel Raynal
2019-08-06 14:54 ` [PATCH 10/20] arm64: dts: marvell: Add AP807-quad " Miquel Raynal
2019-08-06 14:54   ` Miquel Raynal
2019-08-06 14:54 ` [PATCH 11/20] arm64: dts: marvell: Fix CP110 NAND controller node multi-line comment alignment Miquel Raynal
2019-08-06 14:54   ` Miquel Raynal
2019-08-06 14:54 ` [PATCH 12/20] arm64: dts: marvell: Prepare the introduction of CP115 Miquel Raynal
2019-08-06 14:54   ` Miquel Raynal
2019-08-06 14:54 ` [PATCH 13/20] arm64: dts: marvell: Drop PCIe I/O ranges from CP11x file Miquel Raynal
2019-08-06 14:54   ` Miquel Raynal
2019-08-06 14:54 ` [PATCH 14/20] arm64: dts: marvell: Externalize PCIe macros " Miquel Raynal
2019-08-06 14:54   ` Miquel Raynal
2019-08-06 14:54 ` [PATCH 15/20] arm64: dts: marvell: Add support for CP115 Miquel Raynal
2019-08-06 14:54   ` Miquel Raynal
2019-08-06 14:54 ` [PATCH 16/20] dt-bindings: marvell: Declare the CN913x SoC compatibles Miquel Raynal
2019-08-06 14:54   ` Miquel Raynal
2019-08-21 19:37   ` Rob Herring
2019-08-21 19:37     ` Rob Herring
2019-08-24 11:30     ` Miquel Raynal
2019-08-06 14:54 ` Miquel Raynal [this message]
2019-08-06 14:54   ` [PATCH 17/20] arm64: dts: marvell: Add support for Marvell CN9130 SoC support Miquel Raynal
2019-08-06 14:54 ` [PATCH 18/20] arm64: dts: marvell: Add support for Marvell CN9130-DB Miquel Raynal
2019-08-06 14:54   ` Miquel Raynal
2019-08-06 14:54 ` [PATCH 19/20] arm64: dts: marvell: Add support for Marvell CN9131-DB Miquel Raynal
2019-08-06 14:54   ` Miquel Raynal
2019-08-06 14:55 ` [PATCH 20/20] arm64: dts: marvell: Add support for Marvell CN9132-DB Miquel Raynal
2019-08-06 14:55   ` Miquel Raynal

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