From: Anup Patel <Anup.Patel@wdc.com> To: Palmer Dabbelt <palmer@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com>, Paolo Bonzini <pbonzini@redhat.com>, Radim K <rkrcmar@redhat.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de>, Atish Patra <Atish.Patra@wdc.com>, Alistair Francis <Alistair.Francis@wdc.com>, Damien Le Moal <Damien.LeMoal@wdc.com>, Christoph Hellwig <hch@infradead.org>, Anup Patel <anup@brainfault.org>, "kvm@vger.kernel.org" <kvm@vger.kernel.org>, "linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, Anup Patel <Anup.Patel@wdc.com> Subject: [PATCH v5 17/20] RISC-V: KVM: Implement ONE REG interface for FP registers Date: Thu, 22 Aug 2019 08:46:35 +0000 [thread overview] Message-ID: <20190822084131.114764-18-anup.patel@wdc.com> (raw) In-Reply-To: <20190822084131.114764-1-anup.patel@wdc.com> From: Atish Patra <atish.patra@wdc.com> Add a KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctl interface for floating point registers such as F0-F31 and FCSR. This support is added for both 'F' and 'D' extensions. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> --- arch/riscv/include/uapi/asm/kvm.h | 10 +++ arch/riscv/kvm/vcpu.c | 104 ++++++++++++++++++++++++++++++ 2 files changed, 114 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index 024f220eb17e..c9f03363bb28 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -83,6 +83,16 @@ struct kvm_sregs { #define KVM_REG_RISCV_CSR_REG(name) \ (offsetof(struct kvm_sregs, name) / sizeof(unsigned long)) +/* F extension registers are mapped as type4 */ +#define KVM_REG_RISCV_FP_F (0x04 << KVM_REG_RISCV_TYPE_SHIFT) +#define KVM_REG_RISCV_FP_F_REG(name) \ + (offsetof(struct __riscv_f_ext_state, name) / sizeof(u32)) + +/* D extension registers are mapped as type 5 */ +#define KVM_REG_RISCV_FP_D (0x05 << KVM_REG_RISCV_TYPE_SHIFT) +#define KVM_REG_RISCV_FP_D_REG(name) \ + (offsetof(struct __riscv_d_ext_state, name) / sizeof(u64)) + #endif #endif /* __LINUX_KVM_RISCV_H */ diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index e7c5fe09c3bc..ad7b67dc80aa 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -426,6 +426,98 @@ static int kvm_riscv_vcpu_set_reg_csr(struct kvm_vcpu *vcpu, return 0; } +static int kvm_riscv_vcpu_get_reg_fp(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg, + unsigned long rtype) +{ + struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; + unsigned long isa = vcpu->arch.isa; + unsigned long __user *uaddr = + (unsigned long __user *)(unsigned long)reg->addr; + unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | + KVM_REG_SIZE_MASK | + rtype); + void *reg_val; + + if ((rtype == KVM_REG_RISCV_FP_F) && + riscv_isa_extension_available(&isa, f)) { + if (KVM_REG_SIZE(reg->id) != sizeof(u32)) + return -EINVAL; + if (reg_num == KVM_REG_RISCV_FP_F_REG(fcsr)) + reg_val = &cntx->fp.f.fcsr; + else if ((KVM_REG_RISCV_FP_F_REG(f[0]) <= reg_num) && + reg_num <= KVM_REG_RISCV_FP_F_REG(f[31])) + reg_val = &cntx->fp.f.f[reg_num]; + else + return -EINVAL; + } else if ((rtype == KVM_REG_RISCV_FP_D) && + riscv_isa_extension_available(&isa, d)) { + if (reg_num == KVM_REG_RISCV_FP_D_REG(fcsr)) { + if (KVM_REG_SIZE(reg->id) != sizeof(u32)) + return -EINVAL; + reg_val = &cntx->fp.d.fcsr; + } else if ((KVM_REG_RISCV_FP_D_REG(f[0]) <= reg_num) && + reg_num <= KVM_REG_RISCV_FP_D_REG(f[31])) { + if (KVM_REG_SIZE(reg->id) != sizeof(u64)) + return -EINVAL; + reg_val = &cntx->fp.d.f[reg_num]; + } else + return -EINVAL; + } else + return -EINVAL; + + if (copy_to_user(uaddr, reg_val, KVM_REG_SIZE(reg->id))) + return -EFAULT; + + return 0; +} + +static int kvm_riscv_vcpu_set_reg_fp(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg, + unsigned long rtype) +{ + struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; + unsigned long isa = vcpu->arch.isa; + unsigned long __user *uaddr = + (unsigned long __user *)(unsigned long)reg->addr; + unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | + KVM_REG_SIZE_MASK | + rtype); + void *reg_val; + + if ((rtype == KVM_REG_RISCV_FP_F) && + riscv_isa_extension_available(&isa, f)) { + if (KVM_REG_SIZE(reg->id) != sizeof(u32)) + return -EINVAL; + if (reg_num == KVM_REG_RISCV_FP_F_REG(fcsr)) + reg_val = &cntx->fp.f.fcsr; + else if ((KVM_REG_RISCV_FP_F_REG(f[0]) <= reg_num) && + reg_num <= KVM_REG_RISCV_FP_F_REG(f[31])) + reg_val = &cntx->fp.f.f[reg_num]; + else + return -EINVAL; + } else if ((rtype == KVM_REG_RISCV_FP_D) && + riscv_isa_extension_available(&isa, d)) { + if (reg_num == KVM_REG_RISCV_FP_D_REG(fcsr)) { + if (KVM_REG_SIZE(reg->id) != sizeof(u32)) + return -EINVAL; + reg_val = &cntx->fp.d.fcsr; + } else if ((KVM_REG_RISCV_FP_D_REG(f[0]) <= reg_num) && + reg_num <= KVM_REG_RISCV_FP_D_REG(f[31])) { + if (KVM_REG_SIZE(reg->id) != sizeof(u64)) + return -EINVAL; + reg_val = &cntx->fp.d.f[reg_num]; + } else + return -EINVAL; + } else + return -EINVAL; + + if (copy_from_user(reg_val, uaddr, KVM_REG_SIZE(reg->id))) + return -EFAULT; + + return 0; +} + static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) { @@ -435,6 +527,12 @@ static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu, return kvm_riscv_vcpu_set_reg_core(vcpu, reg); else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR) return kvm_riscv_vcpu_set_reg_csr(vcpu, reg); + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F) + return kvm_riscv_vcpu_set_reg_fp(vcpu, reg, + KVM_REG_RISCV_FP_F); + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D) + return kvm_riscv_vcpu_set_reg_fp(vcpu, reg, + KVM_REG_RISCV_FP_D); return -EINVAL; } @@ -448,6 +546,12 @@ static int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu, return kvm_riscv_vcpu_get_reg_core(vcpu, reg); else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR) return kvm_riscv_vcpu_get_reg_csr(vcpu, reg); + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F) + return kvm_riscv_vcpu_get_reg_fp(vcpu, reg, + KVM_REG_RISCV_FP_F); + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D) + return kvm_riscv_vcpu_get_reg_fp(vcpu, reg, + KVM_REG_RISCV_FP_D); return -EINVAL; } -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <Anup.Patel@wdc.com> To: Palmer Dabbelt <palmer@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com>, Paolo Bonzini <pbonzini@redhat.com>, Radim K <rkrcmar@redhat.com> Cc: Damien Le Moal <Damien.LeMoal@wdc.com>, Anup Patel <Anup.Patel@wdc.com>, "kvm@vger.kernel.org" <kvm@vger.kernel.org>, Anup Patel <anup@brainfault.org>, Daniel Lezcano <daniel.lezcano@linaro.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, Christoph Hellwig <hch@infradead.org>, Atish Patra <Atish.Patra@wdc.com>, Alistair Francis <Alistair.Francis@wdc.com>, Thomas Gleixner <tglx@linutronix.de>, "linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org> Subject: [PATCH v5 17/20] RISC-V: KVM: Implement ONE REG interface for FP registers Date: Thu, 22 Aug 2019 08:46:35 +0000 [thread overview] Message-ID: <20190822084131.114764-18-anup.patel@wdc.com> (raw) In-Reply-To: <20190822084131.114764-1-anup.patel@wdc.com> From: Atish Patra <atish.patra@wdc.com> Add a KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctl interface for floating point registers such as F0-F31 and FCSR. This support is added for both 'F' and 'D' extensions. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> --- arch/riscv/include/uapi/asm/kvm.h | 10 +++ arch/riscv/kvm/vcpu.c | 104 ++++++++++++++++++++++++++++++ 2 files changed, 114 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index 024f220eb17e..c9f03363bb28 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -83,6 +83,16 @@ struct kvm_sregs { #define KVM_REG_RISCV_CSR_REG(name) \ (offsetof(struct kvm_sregs, name) / sizeof(unsigned long)) +/* F extension registers are mapped as type4 */ +#define KVM_REG_RISCV_FP_F (0x04 << KVM_REG_RISCV_TYPE_SHIFT) +#define KVM_REG_RISCV_FP_F_REG(name) \ + (offsetof(struct __riscv_f_ext_state, name) / sizeof(u32)) + +/* D extension registers are mapped as type 5 */ +#define KVM_REG_RISCV_FP_D (0x05 << KVM_REG_RISCV_TYPE_SHIFT) +#define KVM_REG_RISCV_FP_D_REG(name) \ + (offsetof(struct __riscv_d_ext_state, name) / sizeof(u64)) + #endif #endif /* __LINUX_KVM_RISCV_H */ diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index e7c5fe09c3bc..ad7b67dc80aa 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -426,6 +426,98 @@ static int kvm_riscv_vcpu_set_reg_csr(struct kvm_vcpu *vcpu, return 0; } +static int kvm_riscv_vcpu_get_reg_fp(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg, + unsigned long rtype) +{ + struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; + unsigned long isa = vcpu->arch.isa; + unsigned long __user *uaddr = + (unsigned long __user *)(unsigned long)reg->addr; + unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | + KVM_REG_SIZE_MASK | + rtype); + void *reg_val; + + if ((rtype == KVM_REG_RISCV_FP_F) && + riscv_isa_extension_available(&isa, f)) { + if (KVM_REG_SIZE(reg->id) != sizeof(u32)) + return -EINVAL; + if (reg_num == KVM_REG_RISCV_FP_F_REG(fcsr)) + reg_val = &cntx->fp.f.fcsr; + else if ((KVM_REG_RISCV_FP_F_REG(f[0]) <= reg_num) && + reg_num <= KVM_REG_RISCV_FP_F_REG(f[31])) + reg_val = &cntx->fp.f.f[reg_num]; + else + return -EINVAL; + } else if ((rtype == KVM_REG_RISCV_FP_D) && + riscv_isa_extension_available(&isa, d)) { + if (reg_num == KVM_REG_RISCV_FP_D_REG(fcsr)) { + if (KVM_REG_SIZE(reg->id) != sizeof(u32)) + return -EINVAL; + reg_val = &cntx->fp.d.fcsr; + } else if ((KVM_REG_RISCV_FP_D_REG(f[0]) <= reg_num) && + reg_num <= KVM_REG_RISCV_FP_D_REG(f[31])) { + if (KVM_REG_SIZE(reg->id) != sizeof(u64)) + return -EINVAL; + reg_val = &cntx->fp.d.f[reg_num]; + } else + return -EINVAL; + } else + return -EINVAL; + + if (copy_to_user(uaddr, reg_val, KVM_REG_SIZE(reg->id))) + return -EFAULT; + + return 0; +} + +static int kvm_riscv_vcpu_set_reg_fp(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg, + unsigned long rtype) +{ + struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; + unsigned long isa = vcpu->arch.isa; + unsigned long __user *uaddr = + (unsigned long __user *)(unsigned long)reg->addr; + unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | + KVM_REG_SIZE_MASK | + rtype); + void *reg_val; + + if ((rtype == KVM_REG_RISCV_FP_F) && + riscv_isa_extension_available(&isa, f)) { + if (KVM_REG_SIZE(reg->id) != sizeof(u32)) + return -EINVAL; + if (reg_num == KVM_REG_RISCV_FP_F_REG(fcsr)) + reg_val = &cntx->fp.f.fcsr; + else if ((KVM_REG_RISCV_FP_F_REG(f[0]) <= reg_num) && + reg_num <= KVM_REG_RISCV_FP_F_REG(f[31])) + reg_val = &cntx->fp.f.f[reg_num]; + else + return -EINVAL; + } else if ((rtype == KVM_REG_RISCV_FP_D) && + riscv_isa_extension_available(&isa, d)) { + if (reg_num == KVM_REG_RISCV_FP_D_REG(fcsr)) { + if (KVM_REG_SIZE(reg->id) != sizeof(u32)) + return -EINVAL; + reg_val = &cntx->fp.d.fcsr; + } else if ((KVM_REG_RISCV_FP_D_REG(f[0]) <= reg_num) && + reg_num <= KVM_REG_RISCV_FP_D_REG(f[31])) { + if (KVM_REG_SIZE(reg->id) != sizeof(u64)) + return -EINVAL; + reg_val = &cntx->fp.d.f[reg_num]; + } else + return -EINVAL; + } else + return -EINVAL; + + if (copy_from_user(reg_val, uaddr, KVM_REG_SIZE(reg->id))) + return -EFAULT; + + return 0; +} + static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) { @@ -435,6 +527,12 @@ static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu, return kvm_riscv_vcpu_set_reg_core(vcpu, reg); else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR) return kvm_riscv_vcpu_set_reg_csr(vcpu, reg); + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F) + return kvm_riscv_vcpu_set_reg_fp(vcpu, reg, + KVM_REG_RISCV_FP_F); + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D) + return kvm_riscv_vcpu_set_reg_fp(vcpu, reg, + KVM_REG_RISCV_FP_D); return -EINVAL; } @@ -448,6 +546,12 @@ static int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu, return kvm_riscv_vcpu_get_reg_core(vcpu, reg); else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR) return kvm_riscv_vcpu_get_reg_csr(vcpu, reg); + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F) + return kvm_riscv_vcpu_get_reg_fp(vcpu, reg, + KVM_REG_RISCV_FP_F); + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D) + return kvm_riscv_vcpu_get_reg_fp(vcpu, reg, + KVM_REG_RISCV_FP_D); return -EINVAL; } -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2019-08-22 8:46 UTC|newest] Thread overview: 122+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-08-22 8:42 [PATCH v5 00/20] KVM RISC-V Support Anup Patel 2019-08-22 8:42 ` Anup Patel 2019-08-22 8:42 ` [PATCH v5 01/20] KVM: RISC-V: Add KVM_REG_RISCV for ONE_REG interface Anup Patel 2019-08-22 8:42 ` Anup Patel 2019-08-22 8:42 ` [PATCH v5 02/20] RISC-V: Add bitmap reprensenting ISA features common across CPUs Anup Patel 2019-08-22 8:42 ` Anup Patel 2019-08-22 8:43 ` [PATCH v5 03/20] RISC-V: Export few kernel symbols Anup Patel 2019-08-22 8:43 ` Anup Patel 2019-08-22 8:43 ` [PATCH v5 04/20] RISC-V: Add hypervisor extension related CSR defines Anup Patel 2019-08-22 8:43 ` Anup Patel 2019-08-22 8:43 ` [PATCH v5 05/20] RISC-V: Add initial skeletal KVM support Anup Patel 2019-08-22 8:43 ` Anup Patel 2019-08-22 8:43 ` [PATCH v5 06/20] RISC-V: KVM: Implement VCPU create, init and destroy functions Anup Patel 2019-08-22 8:43 ` Anup Patel 2019-08-22 8:44 ` [PATCH v5 07/20] RISC-V: KVM: Implement VCPU interrupts and requests handling Anup Patel 2019-08-22 8:44 ` Anup Patel 2019-08-22 8:44 ` [PATCH v5 08/20] RISC-V: KVM: Implement KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls Anup Patel 2019-08-22 8:44 ` Anup Patel 2019-08-22 12:01 ` Alexander Graf 2019-08-22 12:01 ` Alexander Graf 2019-08-22 14:00 ` Anup Patel 2019-08-22 14:00 ` Anup Patel 2019-08-22 14:12 ` Alexander Graf 2019-08-22 14:12 ` Alexander Graf 2019-08-23 11:20 ` Anup Patel 2019-08-23 11:20 ` Anup Patel 2019-08-23 11:42 ` Graf (AWS), Alexander 2019-08-23 11:42 ` Graf (AWS), Alexander 2019-08-22 14:05 ` Anup Patel 2019-08-22 14:05 ` Anup Patel 2019-08-22 8:44 ` [PATCH v5 09/20] RISC-V: KVM: Implement VCPU world-switch Anup Patel 2019-08-22 8:44 ` Anup Patel 2019-08-22 8:44 ` [PATCH v5 10/20] RISC-V: KVM: Handle MMIO exits for VCPU Anup Patel 2019-08-22 8:44 ` Anup Patel 2019-08-22 12:10 ` Alexander Graf 2019-08-22 12:10 ` Alexander Graf 2019-08-22 12:21 ` Andrew Jones 2019-08-22 12:21 ` Andrew Jones 2019-08-22 12:27 ` Anup Patel 2019-08-22 12:27 ` Anup Patel 2019-08-22 12:14 ` Alexander Graf 2019-08-22 12:14 ` Alexander Graf 2019-08-22 12:33 ` Anup Patel 2019-08-22 12:33 ` Anup Patel 2019-08-22 13:25 ` Alexander Graf 2019-08-22 13:25 ` Alexander Graf 2019-08-22 13:55 ` Anup Patel 2019-08-22 13:55 ` Anup Patel 2019-08-22 8:45 ` [PATCH v5 11/20] RISC-V: KVM: Handle WFI " Anup Patel 2019-08-22 8:45 ` Anup Patel 2019-08-22 12:19 ` Alexander Graf 2019-08-22 12:19 ` Alexander Graf 2019-08-22 12:50 ` Anup Patel 2019-08-22 12:50 ` Anup Patel 2019-08-22 8:45 ` [PATCH v5 12/20] RISC-V: KVM: Implement VMID allocator Anup Patel 2019-08-22 8:45 ` Anup Patel 2019-08-22 8:45 ` [PATCH v5 13/20] RISC-V: KVM: Implement stage2 page table programming Anup Patel 2019-08-22 8:45 ` Anup Patel 2019-08-22 12:28 ` Alexander Graf 2019-08-22 12:28 ` Alexander Graf 2019-08-22 12:38 ` Anup Patel 2019-08-22 12:38 ` Anup Patel 2019-08-22 13:27 ` Alexander Graf 2019-08-22 13:27 ` Alexander Graf 2019-08-22 13:58 ` Anup Patel 2019-08-22 13:58 ` Anup Patel 2019-08-22 14:09 ` Alexander Graf 2019-08-22 14:09 ` Alexander Graf 2019-08-23 11:21 ` Anup Patel 2019-08-23 11:21 ` Anup Patel 2019-08-22 8:45 ` [PATCH v5 14/20] RISC-V: KVM: Implement MMU notifiers Anup Patel 2019-08-22 8:45 ` Anup Patel 2019-08-22 8:46 ` [PATCH v5 15/20] RISC-V: KVM: Add timer functionality Anup Patel 2019-08-22 8:46 ` Anup Patel 2019-08-23 7:52 ` Alexander Graf 2019-08-23 7:52 ` Alexander Graf 2019-08-23 11:04 ` Anup Patel 2019-08-23 11:04 ` Anup Patel 2019-08-23 11:33 ` Graf (AWS), Alexander 2019-08-23 11:33 ` Graf (AWS), Alexander 2019-08-23 11:46 ` Anup Patel 2019-08-23 11:46 ` Anup Patel 2019-08-23 11:49 ` Alexander Graf 2019-08-23 11:49 ` Alexander Graf 2019-08-23 12:11 ` Anup Patel 2019-08-23 12:11 ` Anup Patel 2019-08-23 12:25 ` Alexander Graf 2019-08-23 12:25 ` Alexander Graf 2019-08-22 8:46 ` [PATCH v5 16/20] RISC-V: KVM: FP lazy save/restore Anup Patel 2019-08-22 8:46 ` Anup Patel 2019-08-22 8:46 ` Anup Patel [this message] 2019-08-22 8:46 ` [PATCH v5 17/20] RISC-V: KVM: Implement ONE REG interface for FP registers Anup Patel 2019-08-22 8:46 ` [PATCH v5 18/20] RISC-V: KVM: Add SBI v0.1 support Anup Patel 2019-08-22 8:46 ` Anup Patel 2019-08-23 8:04 ` Alexander Graf 2019-08-23 8:04 ` Alexander Graf 2019-08-23 11:17 ` Anup Patel 2019-08-23 11:17 ` Anup Patel 2019-08-23 11:38 ` Graf (AWS), Alexander 2019-08-23 11:38 ` Graf (AWS), Alexander 2019-08-23 12:00 ` Anup Patel 2019-08-23 12:00 ` Anup Patel 2019-08-23 12:19 ` Alexander Graf 2019-08-23 12:19 ` Alexander Graf 2019-08-23 12:28 ` Anup Patel 2019-08-23 12:28 ` Anup Patel 2019-08-22 8:47 ` [PATCH v5 19/20] RISC-V: Enable VIRTIO drivers in RV64 and RV32 defconfig Anup Patel 2019-08-22 8:47 ` Anup Patel 2019-08-22 8:47 ` [PATCH v5 20/20] RISC-V: KVM: Add MAINTAINERS entry Anup Patel 2019-08-22 8:47 ` Anup Patel 2019-08-23 8:08 ` [PATCH v5 00/20] KVM RISC-V Support Alexander Graf 2019-08-23 8:08 ` Alexander Graf 2019-08-23 11:25 ` Anup Patel 2019-08-23 11:25 ` Anup Patel 2019-08-23 11:44 ` Graf (AWS), Alexander 2019-08-23 11:44 ` Graf (AWS), Alexander 2019-08-23 12:10 ` Paolo Bonzini 2019-08-23 12:10 ` Paolo Bonzini 2019-08-23 12:19 ` Anup Patel 2019-08-23 12:19 ` Anup Patel 2019-08-23 12:28 ` Alexander Graf 2019-08-23 12:28 ` Alexander Graf
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