From: Anup Patel <Anup.Patel@wdc.com> To: Palmer Dabbelt <palmer@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com>, Paolo Bonzini <pbonzini@redhat.com>, Radim K <rkrcmar@redhat.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de>, Atish Patra <Atish.Patra@wdc.com>, Alistair Francis <Alistair.Francis@wdc.com>, Damien Le Moal <Damien.LeMoal@wdc.com>, Christoph Hellwig <hch@infradead.org>, Anup Patel <anup@brainfault.org>, "kvm@vger.kernel.org" <kvm@vger.kernel.org>, "linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, Anup Patel <Anup.Patel@wdc.com> Subject: [PATCH v5 18/20] RISC-V: KVM: Add SBI v0.1 support Date: Thu, 22 Aug 2019 08:46:50 +0000 [thread overview] Message-ID: <20190822084131.114764-19-anup.patel@wdc.com> (raw) In-Reply-To: <20190822084131.114764-1-anup.patel@wdc.com> From: Atish Patra <atish.patra@wdc.com> The KVM host kernel running in HS-mode needs to handle SBI calls coming from guest kernel running in VS-mode. This patch adds SBI v0.1 support in KVM RISC-V. All the SBI calls are implemented correctly except remote tlb flushes. For remote TLB flushes, we are doing full TLB flush and this will be optimized in future. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> --- arch/riscv/include/asm/kvm_host.h | 2 + arch/riscv/kvm/Makefile | 2 +- arch/riscv/kvm/vcpu_exit.c | 3 + arch/riscv/kvm/vcpu_sbi.c | 119 ++++++++++++++++++++++++++++++ 4 files changed, 125 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/kvm/vcpu_sbi.c diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h index 2af3a179c08e..0b1eceaef59f 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -241,4 +241,6 @@ bool kvm_riscv_vcpu_has_interrupt(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_power_off(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu); +int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu); + #endif /* __RISCV_KVM_HOST_H__ */ diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile index 3e0c7558320d..b56dc1650d2c 100644 --- a/arch/riscv/kvm/Makefile +++ b/arch/riscv/kvm/Makefile @@ -9,6 +9,6 @@ ccflags-y := -Ivirt/kvm -Iarch/riscv/kvm kvm-objs := $(common-objs-y) kvm-objs += main.o vm.o vmid.o tlb.o mmu.o -kvm-objs += vcpu.o vcpu_exit.o vcpu_switch.o vcpu_timer.o +kvm-objs += vcpu.o vcpu_exit.o vcpu_switch.o vcpu_timer.o vcpu_sbi.o obj-$(CONFIG_KVM) += kvm.o diff --git a/arch/riscv/kvm/vcpu_exit.c b/arch/riscv/kvm/vcpu_exit.c index fbc04fe335ad..87b83fcf9a14 100644 --- a/arch/riscv/kvm/vcpu_exit.c +++ b/arch/riscv/kvm/vcpu_exit.c @@ -534,6 +534,9 @@ int kvm_riscv_vcpu_exit(struct kvm_vcpu *vcpu, struct kvm_run *run, (vcpu->arch.guest_context.hstatus & HSTATUS_STL)) ret = stage2_page_fault(vcpu, run, scause, stval); break; + case EXC_SUPERVISOR_SYSCALL: + if (vcpu->arch.guest_context.hstatus & HSTATUS_SPV) + ret = kvm_riscv_vcpu_sbi_ecall(vcpu); default: break; }; diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c new file mode 100644 index 000000000000..5793202eb514 --- /dev/null +++ b/arch/riscv/kvm/vcpu_sbi.c @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Atish Patra <atish.patra@wdc.com> + */ + +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/kvm_host.h> +#include <asm/csr.h> +#include <asm/kvm_vcpu_timer.h> + +#define SBI_VERSION_MAJOR 0 +#define SBI_VERSION_MINOR 1 + +/* TODO: Handle traps due to unpriv load and redirect it back to VS-mode */ +static unsigned long kvm_sbi_unpriv_load(const unsigned long *addr, + struct kvm_vcpu *vcpu) +{ + unsigned long flags, val; + unsigned long __hstatus, __sstatus; + + local_irq_save(flags); + __hstatus = csr_read(CSR_HSTATUS); + __sstatus = csr_read(CSR_SSTATUS); + csr_write(CSR_HSTATUS, vcpu->arch.guest_context.hstatus | HSTATUS_SPRV); + csr_write(CSR_SSTATUS, vcpu->arch.guest_context.sstatus); + val = *addr; + csr_write(CSR_HSTATUS, __hstatus); + csr_write(CSR_SSTATUS, __sstatus); + local_irq_restore(flags); + + return val; +} + +static void kvm_sbi_system_shutdown(struct kvm_vcpu *vcpu, u32 type) +{ + int i; + struct kvm_vcpu *tmp; + + kvm_for_each_vcpu(i, tmp, vcpu->kvm) + tmp->arch.power_off = true; + kvm_make_all_cpus_request(vcpu->kvm, KVM_REQ_SLEEP); + + memset(&vcpu->run->system_event, 0, sizeof(vcpu->run->system_event)); + vcpu->run->system_event.type = type; + vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; +} + +int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu) +{ + int ret = 1; + u64 next_cycle; + int vcpuid; + struct kvm_vcpu *remote_vcpu; + ulong dhart_mask; + struct kvm_cpu_context *cp = &vcpu->arch.guest_context; + + if (!cp) + return -EINVAL; + switch (cp->a7) { + case SBI_SET_TIMER: +#if __riscv_xlen == 32 + next_cycle = ((u64)cp->a1 << 32) | (u64)cp->a0; +#else + next_cycle = (u64)cp->a0; +#endif + kvm_riscv_vcpu_timer_next_event(vcpu, next_cycle); + break; + case SBI_CONSOLE_PUTCHAR: + /* Not implemented */ + cp->a0 = -ENOTSUPP; + break; + case SBI_CONSOLE_GETCHAR: + /* Not implemented */ + cp->a0 = -ENOTSUPP; + break; + case SBI_CLEAR_IPI: + kvm_riscv_vcpu_unset_interrupt(vcpu, IRQ_S_SOFT); + break; + case SBI_SEND_IPI: + dhart_mask = kvm_sbi_unpriv_load((unsigned long *)cp->a0, vcpu); + for_each_set_bit(vcpuid, &dhart_mask, BITS_PER_LONG) { + remote_vcpu = kvm_get_vcpu_by_id(vcpu->kvm, vcpuid); + kvm_riscv_vcpu_set_interrupt(remote_vcpu, IRQ_S_SOFT); + } + break; + case SBI_SHUTDOWN: + kvm_sbi_system_shutdown(vcpu, KVM_SYSTEM_EVENT_SHUTDOWN); + ret = 0; + break; + case SBI_REMOTE_FENCE_I: + sbi_remote_fence_i(NULL); + break; + /* + * TODO: There should be a way to call remote hfence.bvma. + * Preferred method is now a SBI call. Until then, just flush + * all tlbs. + */ + case SBI_REMOTE_SFENCE_VMA: + /*TODO: Parse vma range.*/ + sbi_remote_sfence_vma(NULL, 0, 0); + break; + case SBI_REMOTE_SFENCE_VMA_ASID: + /*TODO: Parse vma range for given ASID */ + sbi_remote_sfence_vma(NULL, 0, 0); + break; + default: + cp->a0 = ENOTSUPP; + break; + }; + + if (ret >= 0) + cp->sepc += 4; + + return ret; +} -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <Anup.Patel@wdc.com> To: Palmer Dabbelt <palmer@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com>, Paolo Bonzini <pbonzini@redhat.com>, Radim K <rkrcmar@redhat.com> Cc: Damien Le Moal <Damien.LeMoal@wdc.com>, Anup Patel <Anup.Patel@wdc.com>, "kvm@vger.kernel.org" <kvm@vger.kernel.org>, Anup Patel <anup@brainfault.org>, Daniel Lezcano <daniel.lezcano@linaro.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, Christoph Hellwig <hch@infradead.org>, Atish Patra <Atish.Patra@wdc.com>, Alistair Francis <Alistair.Francis@wdc.com>, Thomas Gleixner <tglx@linutronix.de>, "linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org> Subject: [PATCH v5 18/20] RISC-V: KVM: Add SBI v0.1 support Date: Thu, 22 Aug 2019 08:46:50 +0000 [thread overview] Message-ID: <20190822084131.114764-19-anup.patel@wdc.com> (raw) In-Reply-To: <20190822084131.114764-1-anup.patel@wdc.com> From: Atish Patra <atish.patra@wdc.com> The KVM host kernel running in HS-mode needs to handle SBI calls coming from guest kernel running in VS-mode. This patch adds SBI v0.1 support in KVM RISC-V. All the SBI calls are implemented correctly except remote tlb flushes. For remote TLB flushes, we are doing full TLB flush and this will be optimized in future. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> --- arch/riscv/include/asm/kvm_host.h | 2 + arch/riscv/kvm/Makefile | 2 +- arch/riscv/kvm/vcpu_exit.c | 3 + arch/riscv/kvm/vcpu_sbi.c | 119 ++++++++++++++++++++++++++++++ 4 files changed, 125 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/kvm/vcpu_sbi.c diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h index 2af3a179c08e..0b1eceaef59f 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -241,4 +241,6 @@ bool kvm_riscv_vcpu_has_interrupt(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_power_off(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu); +int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu); + #endif /* __RISCV_KVM_HOST_H__ */ diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile index 3e0c7558320d..b56dc1650d2c 100644 --- a/arch/riscv/kvm/Makefile +++ b/arch/riscv/kvm/Makefile @@ -9,6 +9,6 @@ ccflags-y := -Ivirt/kvm -Iarch/riscv/kvm kvm-objs := $(common-objs-y) kvm-objs += main.o vm.o vmid.o tlb.o mmu.o -kvm-objs += vcpu.o vcpu_exit.o vcpu_switch.o vcpu_timer.o +kvm-objs += vcpu.o vcpu_exit.o vcpu_switch.o vcpu_timer.o vcpu_sbi.o obj-$(CONFIG_KVM) += kvm.o diff --git a/arch/riscv/kvm/vcpu_exit.c b/arch/riscv/kvm/vcpu_exit.c index fbc04fe335ad..87b83fcf9a14 100644 --- a/arch/riscv/kvm/vcpu_exit.c +++ b/arch/riscv/kvm/vcpu_exit.c @@ -534,6 +534,9 @@ int kvm_riscv_vcpu_exit(struct kvm_vcpu *vcpu, struct kvm_run *run, (vcpu->arch.guest_context.hstatus & HSTATUS_STL)) ret = stage2_page_fault(vcpu, run, scause, stval); break; + case EXC_SUPERVISOR_SYSCALL: + if (vcpu->arch.guest_context.hstatus & HSTATUS_SPV) + ret = kvm_riscv_vcpu_sbi_ecall(vcpu); default: break; }; diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c new file mode 100644 index 000000000000..5793202eb514 --- /dev/null +++ b/arch/riscv/kvm/vcpu_sbi.c @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Atish Patra <atish.patra@wdc.com> + */ + +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/kvm_host.h> +#include <asm/csr.h> +#include <asm/kvm_vcpu_timer.h> + +#define SBI_VERSION_MAJOR 0 +#define SBI_VERSION_MINOR 1 + +/* TODO: Handle traps due to unpriv load and redirect it back to VS-mode */ +static unsigned long kvm_sbi_unpriv_load(const unsigned long *addr, + struct kvm_vcpu *vcpu) +{ + unsigned long flags, val; + unsigned long __hstatus, __sstatus; + + local_irq_save(flags); + __hstatus = csr_read(CSR_HSTATUS); + __sstatus = csr_read(CSR_SSTATUS); + csr_write(CSR_HSTATUS, vcpu->arch.guest_context.hstatus | HSTATUS_SPRV); + csr_write(CSR_SSTATUS, vcpu->arch.guest_context.sstatus); + val = *addr; + csr_write(CSR_HSTATUS, __hstatus); + csr_write(CSR_SSTATUS, __sstatus); + local_irq_restore(flags); + + return val; +} + +static void kvm_sbi_system_shutdown(struct kvm_vcpu *vcpu, u32 type) +{ + int i; + struct kvm_vcpu *tmp; + + kvm_for_each_vcpu(i, tmp, vcpu->kvm) + tmp->arch.power_off = true; + kvm_make_all_cpus_request(vcpu->kvm, KVM_REQ_SLEEP); + + memset(&vcpu->run->system_event, 0, sizeof(vcpu->run->system_event)); + vcpu->run->system_event.type = type; + vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; +} + +int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu) +{ + int ret = 1; + u64 next_cycle; + int vcpuid; + struct kvm_vcpu *remote_vcpu; + ulong dhart_mask; + struct kvm_cpu_context *cp = &vcpu->arch.guest_context; + + if (!cp) + return -EINVAL; + switch (cp->a7) { + case SBI_SET_TIMER: +#if __riscv_xlen == 32 + next_cycle = ((u64)cp->a1 << 32) | (u64)cp->a0; +#else + next_cycle = (u64)cp->a0; +#endif + kvm_riscv_vcpu_timer_next_event(vcpu, next_cycle); + break; + case SBI_CONSOLE_PUTCHAR: + /* Not implemented */ + cp->a0 = -ENOTSUPP; + break; + case SBI_CONSOLE_GETCHAR: + /* Not implemented */ + cp->a0 = -ENOTSUPP; + break; + case SBI_CLEAR_IPI: + kvm_riscv_vcpu_unset_interrupt(vcpu, IRQ_S_SOFT); + break; + case SBI_SEND_IPI: + dhart_mask = kvm_sbi_unpriv_load((unsigned long *)cp->a0, vcpu); + for_each_set_bit(vcpuid, &dhart_mask, BITS_PER_LONG) { + remote_vcpu = kvm_get_vcpu_by_id(vcpu->kvm, vcpuid); + kvm_riscv_vcpu_set_interrupt(remote_vcpu, IRQ_S_SOFT); + } + break; + case SBI_SHUTDOWN: + kvm_sbi_system_shutdown(vcpu, KVM_SYSTEM_EVENT_SHUTDOWN); + ret = 0; + break; + case SBI_REMOTE_FENCE_I: + sbi_remote_fence_i(NULL); + break; + /* + * TODO: There should be a way to call remote hfence.bvma. + * Preferred method is now a SBI call. Until then, just flush + * all tlbs. + */ + case SBI_REMOTE_SFENCE_VMA: + /*TODO: Parse vma range.*/ + sbi_remote_sfence_vma(NULL, 0, 0); + break; + case SBI_REMOTE_SFENCE_VMA_ASID: + /*TODO: Parse vma range for given ASID */ + sbi_remote_sfence_vma(NULL, 0, 0); + break; + default: + cp->a0 = ENOTSUPP; + break; + }; + + if (ret >= 0) + cp->sepc += 4; + + return ret; +} -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2019-08-22 8:46 UTC|newest] Thread overview: 122+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-08-22 8:42 [PATCH v5 00/20] KVM RISC-V Support Anup Patel 2019-08-22 8:42 ` Anup Patel 2019-08-22 8:42 ` [PATCH v5 01/20] KVM: RISC-V: Add KVM_REG_RISCV for ONE_REG interface Anup Patel 2019-08-22 8:42 ` Anup Patel 2019-08-22 8:42 ` [PATCH v5 02/20] RISC-V: Add bitmap reprensenting ISA features common across CPUs Anup Patel 2019-08-22 8:42 ` Anup Patel 2019-08-22 8:43 ` [PATCH v5 03/20] RISC-V: Export few kernel symbols Anup Patel 2019-08-22 8:43 ` Anup Patel 2019-08-22 8:43 ` [PATCH v5 04/20] RISC-V: Add hypervisor extension related CSR defines Anup Patel 2019-08-22 8:43 ` Anup Patel 2019-08-22 8:43 ` [PATCH v5 05/20] RISC-V: Add initial skeletal KVM support Anup Patel 2019-08-22 8:43 ` Anup Patel 2019-08-22 8:43 ` [PATCH v5 06/20] RISC-V: KVM: Implement VCPU create, init and destroy functions Anup Patel 2019-08-22 8:43 ` Anup Patel 2019-08-22 8:44 ` [PATCH v5 07/20] RISC-V: KVM: Implement VCPU interrupts and requests handling Anup Patel 2019-08-22 8:44 ` Anup Patel 2019-08-22 8:44 ` [PATCH v5 08/20] RISC-V: KVM: Implement KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls Anup Patel 2019-08-22 8:44 ` Anup Patel 2019-08-22 12:01 ` Alexander Graf 2019-08-22 12:01 ` Alexander Graf 2019-08-22 14:00 ` Anup Patel 2019-08-22 14:00 ` Anup Patel 2019-08-22 14:12 ` Alexander Graf 2019-08-22 14:12 ` Alexander Graf 2019-08-23 11:20 ` Anup Patel 2019-08-23 11:20 ` Anup Patel 2019-08-23 11:42 ` Graf (AWS), Alexander 2019-08-23 11:42 ` Graf (AWS), Alexander 2019-08-22 14:05 ` Anup Patel 2019-08-22 14:05 ` Anup Patel 2019-08-22 8:44 ` [PATCH v5 09/20] RISC-V: KVM: Implement VCPU world-switch Anup Patel 2019-08-22 8:44 ` Anup Patel 2019-08-22 8:44 ` [PATCH v5 10/20] RISC-V: KVM: Handle MMIO exits for VCPU Anup Patel 2019-08-22 8:44 ` Anup Patel 2019-08-22 12:10 ` Alexander Graf 2019-08-22 12:10 ` Alexander Graf 2019-08-22 12:21 ` Andrew Jones 2019-08-22 12:21 ` Andrew Jones 2019-08-22 12:27 ` Anup Patel 2019-08-22 12:27 ` Anup Patel 2019-08-22 12:14 ` Alexander Graf 2019-08-22 12:14 ` Alexander Graf 2019-08-22 12:33 ` Anup Patel 2019-08-22 12:33 ` Anup Patel 2019-08-22 13:25 ` Alexander Graf 2019-08-22 13:25 ` Alexander Graf 2019-08-22 13:55 ` Anup Patel 2019-08-22 13:55 ` Anup Patel 2019-08-22 8:45 ` [PATCH v5 11/20] RISC-V: KVM: Handle WFI " Anup Patel 2019-08-22 8:45 ` Anup Patel 2019-08-22 12:19 ` Alexander Graf 2019-08-22 12:19 ` Alexander Graf 2019-08-22 12:50 ` Anup Patel 2019-08-22 12:50 ` Anup Patel 2019-08-22 8:45 ` [PATCH v5 12/20] RISC-V: KVM: Implement VMID allocator Anup Patel 2019-08-22 8:45 ` Anup Patel 2019-08-22 8:45 ` [PATCH v5 13/20] RISC-V: KVM: Implement stage2 page table programming Anup Patel 2019-08-22 8:45 ` Anup Patel 2019-08-22 12:28 ` Alexander Graf 2019-08-22 12:28 ` Alexander Graf 2019-08-22 12:38 ` Anup Patel 2019-08-22 12:38 ` Anup Patel 2019-08-22 13:27 ` Alexander Graf 2019-08-22 13:27 ` Alexander Graf 2019-08-22 13:58 ` Anup Patel 2019-08-22 13:58 ` Anup Patel 2019-08-22 14:09 ` Alexander Graf 2019-08-22 14:09 ` Alexander Graf 2019-08-23 11:21 ` Anup Patel 2019-08-23 11:21 ` Anup Patel 2019-08-22 8:45 ` [PATCH v5 14/20] RISC-V: KVM: Implement MMU notifiers Anup Patel 2019-08-22 8:45 ` Anup Patel 2019-08-22 8:46 ` [PATCH v5 15/20] RISC-V: KVM: Add timer functionality Anup Patel 2019-08-22 8:46 ` Anup Patel 2019-08-23 7:52 ` Alexander Graf 2019-08-23 7:52 ` Alexander Graf 2019-08-23 11:04 ` Anup Patel 2019-08-23 11:04 ` Anup Patel 2019-08-23 11:33 ` Graf (AWS), Alexander 2019-08-23 11:33 ` Graf (AWS), Alexander 2019-08-23 11:46 ` Anup Patel 2019-08-23 11:46 ` Anup Patel 2019-08-23 11:49 ` Alexander Graf 2019-08-23 11:49 ` Alexander Graf 2019-08-23 12:11 ` Anup Patel 2019-08-23 12:11 ` Anup Patel 2019-08-23 12:25 ` Alexander Graf 2019-08-23 12:25 ` Alexander Graf 2019-08-22 8:46 ` [PATCH v5 16/20] RISC-V: KVM: FP lazy save/restore Anup Patel 2019-08-22 8:46 ` Anup Patel 2019-08-22 8:46 ` [PATCH v5 17/20] RISC-V: KVM: Implement ONE REG interface for FP registers Anup Patel 2019-08-22 8:46 ` Anup Patel 2019-08-22 8:46 ` Anup Patel [this message] 2019-08-22 8:46 ` [PATCH v5 18/20] RISC-V: KVM: Add SBI v0.1 support Anup Patel 2019-08-23 8:04 ` Alexander Graf 2019-08-23 8:04 ` Alexander Graf 2019-08-23 11:17 ` Anup Patel 2019-08-23 11:17 ` Anup Patel 2019-08-23 11:38 ` Graf (AWS), Alexander 2019-08-23 11:38 ` Graf (AWS), Alexander 2019-08-23 12:00 ` Anup Patel 2019-08-23 12:00 ` Anup Patel 2019-08-23 12:19 ` Alexander Graf 2019-08-23 12:19 ` Alexander Graf 2019-08-23 12:28 ` Anup Patel 2019-08-23 12:28 ` Anup Patel 2019-08-22 8:47 ` [PATCH v5 19/20] RISC-V: Enable VIRTIO drivers in RV64 and RV32 defconfig Anup Patel 2019-08-22 8:47 ` Anup Patel 2019-08-22 8:47 ` [PATCH v5 20/20] RISC-V: KVM: Add MAINTAINERS entry Anup Patel 2019-08-22 8:47 ` Anup Patel 2019-08-23 8:08 ` [PATCH v5 00/20] KVM RISC-V Support Alexander Graf 2019-08-23 8:08 ` Alexander Graf 2019-08-23 11:25 ` Anup Patel 2019-08-23 11:25 ` Anup Patel 2019-08-23 11:44 ` Graf (AWS), Alexander 2019-08-23 11:44 ` Graf (AWS), Alexander 2019-08-23 12:10 ` Paolo Bonzini 2019-08-23 12:10 ` Paolo Bonzini 2019-08-23 12:19 ` Anup Patel 2019-08-23 12:19 ` Anup Patel 2019-08-23 12:28 ` Alexander Graf 2019-08-23 12:28 ` Alexander Graf
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