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From: Anshuman Gupta <anshuman.gupta@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com
Subject: [RFC 0/7] DC3CO Support for TGL
Date: Fri, 30 Aug 2019 23:14:26 +0530	[thread overview]
Message-ID: <20190830174433.22227-1-anshuman.gupta@intel.com> (raw)

This is a new design proposal for DC3CO feature after disscussing
it with Ville and Imre.

This design uses a API tgl_set_target_dc_state() API
to switch between DC3CO and DC5 by using "DC off"
power well. Another major change in this design using page flip
frontbuffer flush call to allow DC3CO.

As part of DC3CO feature, it needs to configure and enable 
TRANS_EXITLINE register which only needs to change when
transcoder/port is not enabled. It requires to configure and
enable it in full modeset sequence. Which requires to force
the modeset at only at system bootup, with only eDP panel. 
(when system boots with only eDP panel there will not be real
 modeset). I observed sometimes hang while early bootup, which
seems side effect of forcing a modeset at bootup. I am working
to fix it.

Tagging this as RFC series, i need feedback, suggestion and ACK
to this new design.

Anshuman Gupta (7):
  drm/i915/tgl: Add DC3CO required register and bits
  drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
  drm/i915/tgl: Enable DC3CO state in "DC Off" power well
  drm/i915/tgl: Add helper function for DC3CO exitline.
  drm/i915/tgl: DC3CO PSR2 helper
  drm/i915/tgl: switch between dc3co and dc5 based on display idleness
  drm/i915/tgl: Add DC3CO counter in i915_dmc_info

 drivers/gpu/drm/i915/display/intel_display.c  |   4 +
 .../drm/i915/display/intel_display_power.c    | 289 ++++++++++++++++--
 .../drm/i915/display/intel_display_power.h    |  14 +
 .../gpu/drm/i915/display/intel_frontbuffer.c  |   1 +
 drivers/gpu/drm/i915/display/intel_psr.c      |  44 +++
 drivers/gpu/drm/i915/display/intel_psr.h      |   2 +
 drivers/gpu/drm/i915/i915_debugfs.c           |   6 +
 drivers/gpu/drm/i915/i915_drv.h               |   4 +
 drivers/gpu/drm/i915/i915_params.c            |   3 +-
 drivers/gpu/drm/i915/i915_reg.h               |  10 +
 drivers/gpu/drm/i915/intel_pm.c               |   2 +-
 drivers/gpu/drm/i915/intel_pm.h               |   2 +
 12 files changed, 351 insertions(+), 30 deletions(-)

-- 
2.21.0

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             reply	other threads:[~2019-08-30 17:47 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-30 17:44 Anshuman Gupta [this message]
2019-08-30 17:44 ` [RFC 1/7] drm/i915/tgl: Add DC3CO required register and bits Anshuman Gupta
2019-08-30 17:44 ` [RFC 2/7] drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask Anshuman Gupta
2019-08-30 17:44 ` [RFC 3/7] drm/i915/tgl: Enable DC3CO state in "DC Off" power well Anshuman Gupta
2019-08-30 17:44 ` [RFC 4/7] drm/i915/tgl: Add helper function for DC3CO exitline Anshuman Gupta
2019-08-30 17:44 ` [RFC 5/7] drm/i915/tgl: DC3CO PSR2 helper Anshuman Gupta
2019-08-30 17:44 ` [RFC 6/7] drm/i915/tgl: switch between dc3co and dc5 based on display idleness Anshuman Gupta
2019-08-30 17:44 ` [RFC 7/7] drm/i915/tgl: Add DC3CO counter in i915_dmc_info Anshuman Gupta
2019-08-30 18:45 ` ✗ Fi.CI.CHECKPATCH: warning for DC3CO Support for TGL (rev4) Patchwork
2019-08-30 19:09 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-08-31  6:22 ` ✗ Fi.CI.CHECKPATCH: warning for DC3CO Support for TGL (rev5) Patchwork
2019-08-31  6:45 ` ✗ Fi.CI.BAT: failure " Patchwork

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