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From: Anshuman Gupta <anshuman.gupta@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com
Subject: [RFC 1/7] drm/i915/tgl: Add DC3CO required register and bits
Date: Fri, 30 Aug 2019 23:14:27 +0530	[thread overview]
Message-ID: <20190830174433.22227-2-anshuman.gupta@intel.com> (raw)
In-Reply-To: <20190830174433.22227-1-anshuman.gupta@intel.com>

Adding following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
2. Transcoder EXITLINE register and its bit fields and mask.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 02e1ef10c47e..d6b6181c1ffd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4135,6 +4135,7 @@ enum {
 #define _VTOTAL_A	0x6000c
 #define _VBLANK_A	0x60010
 #define _VSYNC_A	0x60014
+#define _EXITLINE_A	0x60018
 #define _PIPEASRC	0x6001c
 #define _BCLRPAT_A	0x60020
 #define _VSYNCSHIFT_A	0x60028
@@ -4181,11 +4182,16 @@ enum {
 #define VTOTAL(trans)		_MMIO_TRANS2(trans, _VTOTAL_A)
 #define VBLANK(trans)		_MMIO_TRANS2(trans, _VBLANK_A)
 #define VSYNC(trans)		_MMIO_TRANS2(trans, _VSYNC_A)
+#define EXITLINE(trans)		_MMIO_TRANS2(trans, _EXITLINE_A)
 #define BCLRPAT(trans)		_MMIO_TRANS2(trans, _BCLRPAT_A)
 #define VSYNCSHIFT(trans)	_MMIO_TRANS2(trans, _VSYNCSHIFT_A)
 #define PIPESRC(trans)		_MMIO_TRANS2(trans, _PIPEASRC)
 #define PIPE_MULT(trans)	_MMIO_TRANS2(trans, _PIPE_MULT_A)
 
+#define  EXITLINE_ENABLE	(1 << 31)
+#define  EXITLINE_MASK		(0x1fff)
+#define  EXITLINE_SHIFT		0
+
 /*
  * HSW+ eDP PSR registers
  *
@@ -10005,6 +10011,8 @@ enum skl_power_gate {
 /* GEN9 DC */
 #define DC_STATE_EN			_MMIO(0x45504)
 #define  DC_STATE_DISABLE		0
+#define  DC_STATE_EN_DC3CO		(1 << 30)
+#define  DC_STATE_DC3CO_STATUS		(1 << 29)
 #define  DC_STATE_EN_UPTO_DC5		(1 << 0)
 #define  DC_STATE_EN_DC9		(1 << 3)
 #define  DC_STATE_EN_UPTO_DC6		(2 << 0)
-- 
2.21.0

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  reply	other threads:[~2019-08-30 17:47 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-30 17:44 [RFC 0/7] DC3CO Support for TGL Anshuman Gupta
2019-08-30 17:44 ` Anshuman Gupta [this message]
2019-08-30 17:44 ` [RFC 2/7] drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask Anshuman Gupta
2019-08-30 17:44 ` [RFC 3/7] drm/i915/tgl: Enable DC3CO state in "DC Off" power well Anshuman Gupta
2019-08-30 17:44 ` [RFC 4/7] drm/i915/tgl: Add helper function for DC3CO exitline Anshuman Gupta
2019-08-30 17:44 ` [RFC 5/7] drm/i915/tgl: DC3CO PSR2 helper Anshuman Gupta
2019-08-30 17:44 ` [RFC 6/7] drm/i915/tgl: switch between dc3co and dc5 based on display idleness Anshuman Gupta
2019-08-30 17:44 ` [RFC 7/7] drm/i915/tgl: Add DC3CO counter in i915_dmc_info Anshuman Gupta
2019-08-30 18:45 ` ✗ Fi.CI.CHECKPATCH: warning for DC3CO Support for TGL (rev4) Patchwork
2019-08-30 19:09 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-08-31  6:22 ` ✗ Fi.CI.CHECKPATCH: warning for DC3CO Support for TGL (rev5) Patchwork
2019-08-31  6:45 ` ✗ Fi.CI.BAT: failure " Patchwork

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