From: Anshuman Gupta <anshuman.gupta@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com
Subject: [PATCH v7 7/7] drm/i915/tgl: Add DC3CO counter in i915_dmc_info
Date: Sat, 7 Sep 2019 22:44:43 +0530 [thread overview]
Message-ID: <20190907171443.16181-8-anshuman.gupta@intel.com> (raw)
In-Reply-To: <20190907171443.16181-1-anshuman.gupta@intel.com>
Adding DC3CO counter in i915_dmc_info debugfs will be
useful for DC3CO validation.
DMC firmware uses DMC_DEBUG3 register as DC3CO counter
register on TGL, as per B.Specs DMC_DEBUG3 is general
purpose register.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 ++++++
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 708855e051b5..161c4bcd3756 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2397,6 +2397,12 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
CSR_VERSION_MINOR(csr->version));
+ /*
+ * TGL DMC f/w uses DMC_DEBUG3 register for DC3CO counter.
+ */
+ if (IS_TIGERLAKE(dev_priv))
+ seq_printf(m, "DC3CO count: %d\n", I915_READ(DMC_DEBUG3));
+
if (INTEL_GEN(dev_priv) >= 12) {
dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 273a4ed8b3e9..0fb86a78c4a4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7251,6 +7251,8 @@ enum {
#define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
#define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)
+#define DMC_DEBUG3 _MMIO(0x101090)
+
/* interrupts */
#define DE_MASTER_IRQ_CONTROL (1 << 31)
#define DE_SPRITEB_FLIP_DONE (1 << 29)
--
2.21.0
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next prev parent reply other threads:[~2019-09-07 17:21 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-07 17:14 [PATCH v7 0/7] DC3CO Support for TGL Anshuman Gupta
2019-09-07 17:14 ` [PATCH v7 1/7] drm/i915/tgl: Add DC3CO required register and bits Anshuman Gupta
2019-09-11 9:08 ` Animesh Manna
2019-09-07 17:14 ` [PATCH v7 2/7] drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask Anshuman Gupta
2019-09-11 9:12 ` Animesh Manna
2019-09-07 17:14 ` [PATCH v7 3/7] drm/i915/tgl: Enable DC3CO state in "DC Off" power well Anshuman Gupta
2019-09-08 16:44 ` Imre Deak
2019-09-09 16:19 ` Anshuman Gupta
2019-09-11 8:21 ` Imre Deak
2019-09-11 12:42 ` Anshuman Gupta
2019-09-07 17:14 ` [PATCH v7 4/7] drm/i915/tgl: Do modeset to enable and configure DC3CO exitline Anshuman Gupta
2019-09-08 17:10 ` Imre Deak
2019-09-07 17:14 ` [PATCH v7 5/7] drm/i915/tgl: DC3CO PSR2 helper Anshuman Gupta
2019-09-08 17:20 ` Imre Deak
2019-09-07 17:14 ` [PATCH v7 6/7] drm/i915/tgl: switch between dc3co and dc5 based on display idleness Anshuman Gupta
2019-09-08 17:55 ` Imre Deak
2019-09-10 9:56 ` Anshuman Gupta
2019-09-11 8:50 ` Imre Deak
2019-09-11 9:57 ` Anshuman Gupta
2019-09-07 17:14 ` Anshuman Gupta [this message]
2019-09-07 17:34 ` ✗ Fi.CI.CHECKPATCH: warning for DC3CO Support for TGL (rev7) Patchwork
2019-09-07 17:37 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-09-07 17:58 ` ✓ Fi.CI.BAT: success " Patchwork
2019-09-07 19:03 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-09-08 5:46 ` ✗ Fi.CI.CHECKPATCH: warning for DC3CO Support for TGL (rev8) Patchwork
2019-09-08 5:49 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-09-08 6:10 ` ✓ Fi.CI.BAT: success " Patchwork
2019-09-08 7:19 ` ✓ Fi.CI.IGT: " Patchwork
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