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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 4/4] drm/i915: Remove duplicated bxt/cnl/icl .modeset_calc_cdclk() funcs
Date: Wed, 11 Sep 2019 16:31:29 +0300	[thread overview]
Message-ID: <20190911133129.27466-4-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20190911133129.27466-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reuse the same .modeset_calc_cdclk() function for all bxt+.

The only difference in between the cnl/icl and the bxt variants
is the call to cnl_compute_min_voltage_level(). We can do that call
just fine on older platforms since they leave min_voltage_level[]
zeroed. Let's rename the function to bxt_compute_min_voltage_level()
just so it stays consistent with the rest of the naming scheme.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 46 +++++-----------------
 1 file changed, 9 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index f5a99eb77efa..b8b3814ba116 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2017,6 +2017,10 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
 }
 
 /*
+ * Account for port clock min voltage level requirements.
+ * This only really does something on CNL+ but can be
+ * called on earlier platforms as well.
+ *
  * Note that this functions assumes that 0 is
  * the lowest voltage value, and higher values
  * correspond to increasingly higher voltages.
@@ -2025,7 +2029,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
  * future platforms this code will need to be
  * adjusted.
  */
-static u8 cnl_compute_min_voltage_level(struct intel_atomic_state *state)
+static u8 bxt_compute_min_voltage_level(struct intel_atomic_state *state)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	struct intel_crtc *crtc;
@@ -2195,43 +2199,11 @@ static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
 	cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
 	vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
 
-	state->cdclk.logical.vco = vco;
-	state->cdclk.logical.cdclk = cdclk;
-	state->cdclk.logical.voltage_level =
-		dev_priv->display.calc_voltage_level(cdclk);
-
-	if (!state->active_pipes) {
-		cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
-		vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
-
-		state->cdclk.actual.vco = vco;
-		state->cdclk.actual.cdclk = cdclk;
-		state->cdclk.actual.voltage_level =
-			dev_priv->display.calc_voltage_level(cdclk);
-	} else {
-		state->cdclk.actual = state->cdclk.logical;
-	}
-
-	return 0;
-}
-
-static int cnl_modeset_calc_cdclk(struct intel_atomic_state *state)
-{
-	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-	int min_cdclk, cdclk, vco;
-
-	min_cdclk = intel_compute_min_cdclk(state);
-	if (min_cdclk < 0)
-		return min_cdclk;
-
-	cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
-	vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
-
 	state->cdclk.logical.vco = vco;
 	state->cdclk.logical.cdclk = cdclk;
 	state->cdclk.logical.voltage_level =
 		max(dev_priv->display.calc_voltage_level(cdclk),
-		    cnl_compute_min_voltage_level(state));
+		    bxt_compute_min_voltage_level(state));
 
 	if (!state->active_pipes) {
 		cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
@@ -2466,17 +2438,17 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 {
 	if (IS_ELKHARTLAKE(dev_priv)) {
 		dev_priv->display.set_cdclk = bxt_set_cdclk;
-		dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
+		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
 		dev_priv->display.calc_voltage_level = ehl_calc_voltage_level;
 		dev_priv->cdclk.table = icl_cdclk_table;
 	} else if (INTEL_GEN(dev_priv) >= 11) {
 		dev_priv->display.set_cdclk = bxt_set_cdclk;
-		dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
+		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
 		dev_priv->display.calc_voltage_level = icl_calc_voltage_level;
 		dev_priv->cdclk.table = icl_cdclk_table;
 	} else if (IS_CANNONLAKE(dev_priv)) {
 		dev_priv->display.set_cdclk = bxt_set_cdclk;
-		dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
+		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
 		dev_priv->display.calc_voltage_level = cnl_calc_voltage_level;
 		dev_priv->cdclk.table = cnl_cdclk_table;
 	} else if (IS_GEN9_LP(dev_priv)) {
-- 
2.21.0

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  parent reply	other threads:[~2019-09-11 13:31 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-11 13:31 [PATCH 1/4] drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk Ville Syrjala
2019-09-11 13:31 ` [PATCH 2/4] drm/i915: Fix CD2X pipe select masking during cdclk sanitation Ville Syrjala
2019-09-11 15:00   ` Matt Roper
2019-09-11 15:08     ` Chris Wilson
2019-09-11 19:03       ` Saarinen, Jani
2019-09-11 15:10     ` Jani Nikula
2019-09-11 19:02     ` Saarinen, Jani
2019-09-11 13:31 ` [PATCH 3/4] drm/i915: Reuse cnl_modeset_calc_cdclk() on icl+ Ville Syrjala
2019-09-11 15:03   ` Matt Roper
2019-09-11 13:31 ` Ville Syrjala [this message]
2019-09-11 15:13   ` [PATCH 4/4] drm/i915: Remove duplicated bxt/cnl/icl .modeset_calc_cdclk() funcs Matt Roper
2019-09-11 14:47 ` [PATCH 1/4] drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk Matt Roper
2019-09-11 15:34 ` ✓ Fi.CI.BAT: success for series starting with [1/4] " Patchwork
2019-09-12  2:31 ` ✓ Fi.CI.IGT: " Patchwork
2019-09-12  9:36 ` ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk (rev2) Patchwork
2019-09-12  9:43   ` Chris Wilson
2019-09-12 16:02 ` ✓ Fi.CI.IGT: " Patchwork

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