From: Julien Grall <julien.grall@arm.com>
To: xen-devel@lists.xenproject.org
Cc: Ross Lagerwall <ross.lagerwall@citrix.com>,
Julien Grall <julien.grall@arm.com>,
Stefano Stabellini <sstabellini@kernel.org>,
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com>,
Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Subject: [Xen-devel] [PATCH for-4.13] xen/arm: livepatch: Prevent CPUs to fetch stale instructions after livepatching
Date: Wed, 18 Sep 2019 14:52:56 +0100 [thread overview]
Message-ID: <20190918135256.7287-1-julien.grall@arm.com> (raw)
During livepatch, a single CPU will take care of applying the patch and
all the others will wait for the action to complete. They will then once
execute arch_livepatch_post_action() to flush the pipeline.
Per B2.2.5 "Concurrent modification and execution of instructions" in
DDI 0487E.a, flushing the instruction cache is not enough to ensure new
instructions are seen. All the PEs should also do an isb() to
synchronize the fetched instruction stream.
Signed-off-by: Julien Grall <julien.grall@arm.com>
---
xen/arch/arm/livepatch.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/xen/arch/arm/livepatch.c b/xen/arch/arm/livepatch.c
index 279d52cc6c..00c5e2bc45 100644
--- a/xen/arch/arm/livepatch.c
+++ b/xen/arch/arm/livepatch.c
@@ -88,7 +88,8 @@ void arch_livepatch_revert(const struct livepatch_func *func)
void arch_livepatch_post_action(void)
{
- /* arch_livepatch_revive has nuked the instruction cache. */
+ /* Discard any stale instructions that may have been fetched. */
+ isb();
}
void arch_livepatch_mask(void)
--
2.11.0
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next reply other threads:[~2019-09-18 13:53 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-18 13:52 Julien Grall [this message]
2019-09-18 15:06 ` [Xen-devel] [PATCH for-4.13] xen/arm: livepatch: Prevent CPUs to fetch stale instructions after livepatching Ross Lagerwall
2019-09-18 16:21 ` Volodymyr Babchuk
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