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From: "Michał Winiarski" <michal.winiarski@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@intel.com>
Subject: [PATCH 3/6] drm/i915: Adjust length of MI_LOAD_REGISTER_REG
Date: Thu, 26 Sep 2019 12:06:32 +0200	[thread overview]
Message-ID: <20190926100635.9416-3-michal.winiarski@intel.com> (raw)
In-Reply-To: <20190926100635.9416-1-michal.winiarski@intel.com>

Default length value of MI_LOAD_REGISTER_REG is 1.
Also move it out of cmd-parser-only registers since we're going to use
it in i915.

Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index f78b13d74e17..9211b1ad401b 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -152,6 +152,7 @@
 #define   MI_FLUSH_DW_USE_PPGTT		(0<<2)
 #define MI_LOAD_REGISTER_MEM	   MI_INSTR(0x29, 1)
 #define MI_LOAD_REGISTER_MEM_GEN8  MI_INSTR(0x29, 2)
+#define MI_LOAD_REGISTER_REG    MI_INSTR(0x2A, 1)
 #define MI_BATCH_BUFFER		MI_INSTR(0x30, 1)
 #define   MI_BATCH_NON_SECURE		(1)
 /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
@@ -256,7 +257,6 @@
 #define MI_CLFLUSH              MI_INSTR(0x27, 0)
 #define MI_REPORT_PERF_COUNT    MI_INSTR(0x28, 0)
 #define   MI_REPORT_PERF_COUNT_GGTT (1<<0)
-#define MI_LOAD_REGISTER_REG    MI_INSTR(0x2A, 0)
 #define MI_RS_STORE_DATA_IMM    MI_INSTR(0x2B, 0)
 #define MI_LOAD_URB_MEM         MI_INSTR(0x2C, 0)
 #define MI_STORE_URB_MEM        MI_INSTR(0x2D, 0)
-- 
2.21.0

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  parent reply	other threads:[~2019-09-26 10:06 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-26 10:06 [PATCH 1/6] drm/i915: Define explicit wedged on init reset state Michał Winiarski
2019-09-26 10:06 ` [PATCH 2/6] drm/i915/execlists: Use per-process HWSP as scratch Michał Winiarski
2019-09-26 10:18   ` Chris Wilson
2019-09-26 10:06 ` Michał Winiarski [this message]
2019-09-26 10:15   ` [PATCH 3/6] drm/i915: Adjust length of MI_LOAD_REGISTER_REG Chris Wilson
2019-09-26 10:06 ` [PATCH 4/6] drm/i915: Add definitions for MI_MATH command Michał Winiarski
2019-09-26 13:25   ` Chris Wilson
2019-09-26 10:06 ` [PATCH 5/6] drm/i915: Don't use scratch in WA batch Michał Winiarski
2019-09-26 10:24   ` Chris Wilson
2019-09-26 18:24     ` Chris Wilson
2019-09-26 13:31   ` Chris Wilson
2019-09-26 10:06 ` [PATCH 6/6] drm/i915/execlists: Don't allocate scratch Michał Winiarski
2019-09-26 10:34   ` Chris Wilson
2019-09-26 12:20   ` [PATCH v2 " Michał Winiarski
2019-09-26 13:26     ` Chris Wilson
2019-09-26 10:20 ` [PATCH 1/6] drm/i915: Define explicit wedged on init reset state Chris Wilson
2019-09-26 10:33 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] " Patchwork
2019-09-26 10:56 ` ✓ Fi.CI.BAT: success " Patchwork
2019-09-26 12:28 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915: Define explicit wedged on init reset state (rev2) Patchwork
2019-09-26 13:14 ` ✗ Fi.CI.BAT: failure " Patchwork

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