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From: Animesh Manna <animesh.manna@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com
Subject: [RFC 6/6] drm/i915/dp: Program vswing, pre-emphasis, test-pattern
Date: Thu,  3 Oct 2019 20:36:53 +0530	[thread overview]
Message-ID: <20191003150653.15881-7-animesh.manna@intel.com> (raw)
In-Reply-To: <20191003150653.15881-1-animesh.manna@intel.com>

This patch process phy compliance request by programming requested
vswing, pre-emphasis and test pattern.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 62 +++++++++++++++++++++++++
 1 file changed, 62 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 93b1ce80c174..dd4c3a81c11d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4817,14 +4817,76 @@ static inline void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
 	}
 }
 
+static void
+intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = intel_dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	enum port port = intel_dig_port->base.port;
+	u32 ddi_buf_ctl_value, dp_tp_ctl_value, trans_ddi_func_ctl_value;
+
+	ddi_buf_ctl_value = I915_READ(DDI_BUF_CTL(port));
+	dp_tp_ctl_value = I915_READ(DP_TP_CTL(port));
+	trans_ddi_func_ctl_value = I915_READ(TRANS_DDI_FUNC_CTL(port));
+
+	ddi_buf_ctl_value        &= ~(DDI_BUF_CTL_ENABLE | DDI_PORT_WIDTH_MASK);
+	dp_tp_ctl_value          &= ~DP_TP_CTL_ENABLE;
+	trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
+				      DDI_PORT_WIDTH_MASK);
+
+	I915_WRITE(DDI_BUF_CTL(port), ddi_buf_ctl_value);
+	I915_WRITE(DP_TP_CTL(port), dp_tp_ctl_value);
+	I915_WRITE(TRANS_DDI_FUNC_CTL(port), trans_ddi_func_ctl_value);
+}
+
+static void
+intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = intel_dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	enum port port = intel_dig_port->base.port;
+	u32 ddi_buf_ctl_value, dp_tp_ctl_value, trans_ddi_func_ctl_value;
+
+	ddi_buf_ctl_value = I915_READ(DDI_BUF_CTL(port));
+	dp_tp_ctl_value = I915_READ(DP_TP_CTL(port));
+	trans_ddi_func_ctl_value = I915_READ(TRANS_DDI_FUNC_CTL(port));
+
+	ddi_buf_ctl_value        |= DDI_BUF_CTL_ENABLE |
+				    DDI_PORT_WIDTH(lane_cnt);
+	dp_tp_ctl_value          |= DP_TP_CTL_ENABLE;
+	trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
+				    DDI_PORT_WIDTH(lane_cnt);
+
+	I915_WRITE(TRANS_DDI_FUNC_CTL(port), trans_ddi_func_ctl_value);
+	I915_WRITE(DP_TP_CTL(port), dp_tp_ctl_value);
+	I915_WRITE(DDI_BUF_CTL(port), ddi_buf_ctl_value);
+}
+
 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
 {
 	u8 test_result = DP_TEST_NAK;
+	struct drm_dp_phy_test_params *data =
+		&intel_dp->compliance.test_data.phytest;
 
 	test_result = intel_dp_prepare_phytest(intel_dp);
 	if (test_result != DP_TEST_ACK)
 		DRM_ERROR("Phy test preparation failed\n");
 
+	intel_dp_autotest_phy_ddi_disable(intel_dp);
+
+	intel_dp_set_signal_levels(intel_dp);
+
+	intel_dp_phy_pattern_update(intel_dp);
+
+	intel_dp_autotest_phy_ddi_enable(intel_dp, data->link.num_lanes);
+
+	drm_dp_set_phy_test_pattern(&intel_dp->aux, data);
+
+	/* Set test active flag here so userspace doesn't interrupt things */
+	intel_dp->compliance.test_active = 1;
+
 	return test_result;
 }
 
-- 
2.22.0

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  parent reply	other threads:[~2019-10-03 15:15 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-03 15:06 [RFC 0/6] DP Phy compliace auto test Animesh Manna
2019-10-03 15:06 ` [RFC 1/6] drm/dp: get/set phy compliance pattern Animesh Manna
2019-10-03 16:24   ` [Intel-gfx] " kbuild test robot
2019-10-21 23:27   ` Manasi Navare
2019-10-22 13:29     ` Animesh Manna
2019-11-05 23:12   ` Manasi Navare
2019-11-05 23:12     ` [Intel-gfx] " Manasi Navare
2019-10-03 15:06 ` [RFC 2/6] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation Animesh Manna
2019-10-21 22:57   ` Manasi Navare
2019-10-22 14:04     ` Animesh Manna
2019-10-22 17:40       ` Manasi Navare
2019-10-24 11:45         ` Animesh Manna
2019-10-24 11:45           ` [Intel-gfx] " Animesh Manna
2019-10-03 15:06 ` [RFC 3/6] drm/i915/dp: Preparation for DP phy compliance auto test Animesh Manna
2019-10-21 23:29   ` Manasi Navare
2019-10-22 14:12     ` Animesh Manna
2019-10-03 15:06 ` [RFC 4/6] drm/i915/dp: Register definition for DP compliance register Animesh Manna
2019-10-03 15:06 ` [RFC 5/6] drm/i915/dp: Update the pattern as per request Animesh Manna
2019-10-03 15:06 ` Animesh Manna [this message]
2019-10-21 23:47   ` [RFC 6/6] drm/i915/dp: Program vswing, pre-emphasis, test-pattern Manasi Navare
2019-10-22 15:07     ` Animesh Manna
2019-10-22 18:41       ` Manasi Navare
2019-10-03 17:36 ` ✓ Fi.CI.BAT: success for DP Phy compliace auto test Patchwork
2019-10-04  3:07 ` ✗ Fi.CI.IGT: failure " Patchwork

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