From: Miquel Raynal <miquel.raynal@bootlin.com> To: Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org, Yan Markman <ymarkman@marvell.com>, Antoine Tenart <antoine.tenart@bootlin.com>, Grzegorz Jaszczyk <jaz@semihalf.com>, Gregory Clement <gregory.clement@bootlin.com>, Maxime Chevallier <maxime.chevallier@bootlin.com>, Nadav Haklai <nadavh@marvell.com>, Thomas Petazzoni <thomas.petazzoni@bootlin.com>, Miquel Raynal <miquel.raynal@bootlin.com>, Stefan Chulski <stefanc@marvell.com>, Marcin Wojtas <mw@semihalf.com>, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 13/21] arm64: dts: marvell: Drop PCIe I/O ranges from CP11x file Date: Fri, 4 Oct 2019 16:27:30 +0200 [thread overview] Message-ID: <20191004142738.7370-14-miquel.raynal@bootlin.com> (raw) In-Reply-To: <20191004142738.7370-1-miquel.raynal@bootlin.com> As an example, Armada 70x0 and 80x0 SoC 0xf9000000 region points to RUNIT/SPICS0 while it is referenced in the DT as PCIe I/O memory range. This shows that I/O memory has never been used/working on the old SoCs despite the region being advertised. As PCIe I/O ranges will not be supported in newer SoCs using CP11x co-processors, let's simply drop them. It is not harmful in any case as PCIe device drivers can do it all with the regular mapped memory anyway. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> --- arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 2 -- .../boot/dts/marvell/armada-8040-mcbin.dtsi | 3 +-- arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 4 ---- arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 16 +++------------- 4 files changed, 4 insertions(+), 21 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi index 4e78ccd207b7..ac28903ea409 100644 --- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi @@ -19,7 +19,6 @@ */ #define CP11X_NAME cp0 #define CP11X_BASE f2000000 -#define CP11X_PCIE_IO_BASE 0xf9000000 #define CP11X_PCIE_MEM_BASE 0xf6000000 #define CP11X_PCIE0_BASE f2600000 #define CP11X_PCIE1_BASE f2620000 @@ -29,7 +28,6 @@ #undef CP11X_NAME #undef CP11X_BASE -#undef CP11X_PCIE_IO_BASE #undef CP11X_PCIE_MEM_BASE #undef CP11X_PCIE0_BASE #undef CP11X_PCIE1_BASE diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi index d250f4b2bfed..572e2610e0a3 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi @@ -179,8 +179,7 @@ num-lanes = <4>; num-viewport = <8>; reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>; - ranges = <0x81000000 0x0 0xf9010000 0x0 0xf9010000 0x0 0x10000 - 0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>; + ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>; phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>; phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy", diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi index ebb98836ec9c..902eed571bcc 100644 --- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi @@ -21,7 +21,6 @@ */ #define CP11X_NAME cp0 #define CP11X_BASE f2000000 -#define CP11X_PCIE_IO_BASE 0xf9000000 #define CP11X_PCIE_MEM_BASE 0xf6000000 #define CP11X_PCIE0_BASE f2600000 #define CP11X_PCIE1_BASE f2620000 @@ -31,7 +30,6 @@ #undef CP11X_NAME #undef CP11X_BASE -#undef CP11X_PCIE_IO_BASE #undef CP11X_PCIE_MEM_BASE #undef CP11X_PCIE0_BASE #undef CP11X_PCIE1_BASE @@ -42,7 +40,6 @@ */ #define CP11X_NAME cp1 #define CP11X_BASE f4000000 -#define CP11X_PCIE_IO_BASE 0xfd000000 #define CP11X_PCIE_MEM_BASE 0xfa000000 #define CP11X_PCIE0_BASE f4600000 #define CP11X_PCIE1_BASE f4620000 @@ -52,7 +49,6 @@ #undef CP11X_NAME #undef CP11X_BASE -#undef CP11X_PCIE_IO_BASE #undef CP11X_PCIE_MEM_BASE #undef CP11X_PCIE0_BASE #undef CP11X_PCIE1_BASE diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi index 3e77cf34604c..7d1ab097453d 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi @@ -10,7 +10,6 @@ #include "armada-common.dtsi" -#define CP11X_PCIEx_IO_BASE(iface) (CP11X_PCIE_IO_BASE + (iface * 0x10000)) #define CP11X_PCIEx_MEM_BASE(iface) (CP11X_PCIE_MEM_BASE + (iface * 0x1000000)) #define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + 0xf00000) @@ -507,11 +506,8 @@ msi-parent = <&gic_v2m0>; bus-range = <0 0xff>; - ranges = - /* downstream I/O */ - <0x81000000 0 CP11X_PCIEx_IO_BASE(0) 0 CP11X_PCIEx_IO_BASE(0) 0 0x10000 /* non-prefetchable memory */ - 0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 0xf00000>; + ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 0xf00000>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; @@ -534,11 +530,8 @@ msi-parent = <&gic_v2m0>; bus-range = <0 0xff>; - ranges = - /* downstream I/O */ - <0x81000000 0 CP11X_PCIEx_IO_BASE(1) 0 CP11X_PCIEx_IO_BASE(1) 0 0x10000 /* non-prefetchable memory */ - 0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 0xf00000>; + ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 0xf00000>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>; interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; @@ -562,11 +555,8 @@ msi-parent = <&gic_v2m0>; bus-range = <0 0xff>; - ranges = - /* downstream I/O */ - <0x81000000 0 CP11X_PCIEx_IO_BASE(2) 0 CP11X_PCIEx_IO_BASE(2) 0 0x10000 /* non-prefetchable memory */ - 0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 0xf00000>; + ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 0xf00000>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Miquel Raynal <miquel.raynal@bootlin.com> To: Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org, Yan Markman <ymarkman@marvell.com>, Antoine Tenart <antoine.tenart@bootlin.com>, Grzegorz Jaszczyk <jaz@semihalf.com>, Gregory Clement <gregory.clement@bootlin.com>, Maxime Chevallier <maxime.chevallier@bootlin.com>, Nadav Haklai <nadavh@marvell.com>, Thomas Petazzoni <thomas.petazzoni@bootlin.com>, Miquel Raynal <miquel.raynal@bootlin.com>, Stefan Chulski <stefanc@marvell.com>, Marcin Wojtas <mw@semihalf.com>, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 13/21] arm64: dts: marvell: Drop PCIe I/O ranges from CP11x file Date: Fri, 4 Oct 2019 16:27:30 +0200 [thread overview] Message-ID: <20191004142738.7370-14-miquel.raynal@bootlin.com> (raw) In-Reply-To: <20191004142738.7370-1-miquel.raynal@bootlin.com> As an example, Armada 70x0 and 80x0 SoC 0xf9000000 region points to RUNIT/SPICS0 while it is referenced in the DT as PCIe I/O memory range. This shows that I/O memory has never been used/working on the old SoCs despite the region being advertised. As PCIe I/O ranges will not be supported in newer SoCs using CP11x co-processors, let's simply drop them. It is not harmful in any case as PCIe device drivers can do it all with the regular mapped memory anyway. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> --- arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 2 -- .../boot/dts/marvell/armada-8040-mcbin.dtsi | 3 +-- arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 4 ---- arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 16 +++------------- 4 files changed, 4 insertions(+), 21 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi index 4e78ccd207b7..ac28903ea409 100644 --- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi @@ -19,7 +19,6 @@ */ #define CP11X_NAME cp0 #define CP11X_BASE f2000000 -#define CP11X_PCIE_IO_BASE 0xf9000000 #define CP11X_PCIE_MEM_BASE 0xf6000000 #define CP11X_PCIE0_BASE f2600000 #define CP11X_PCIE1_BASE f2620000 @@ -29,7 +28,6 @@ #undef CP11X_NAME #undef CP11X_BASE -#undef CP11X_PCIE_IO_BASE #undef CP11X_PCIE_MEM_BASE #undef CP11X_PCIE0_BASE #undef CP11X_PCIE1_BASE diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi index d250f4b2bfed..572e2610e0a3 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi @@ -179,8 +179,7 @@ num-lanes = <4>; num-viewport = <8>; reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>; - ranges = <0x81000000 0x0 0xf9010000 0x0 0xf9010000 0x0 0x10000 - 0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>; + ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>; phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>; phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy", diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi index ebb98836ec9c..902eed571bcc 100644 --- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi @@ -21,7 +21,6 @@ */ #define CP11X_NAME cp0 #define CP11X_BASE f2000000 -#define CP11X_PCIE_IO_BASE 0xf9000000 #define CP11X_PCIE_MEM_BASE 0xf6000000 #define CP11X_PCIE0_BASE f2600000 #define CP11X_PCIE1_BASE f2620000 @@ -31,7 +30,6 @@ #undef CP11X_NAME #undef CP11X_BASE -#undef CP11X_PCIE_IO_BASE #undef CP11X_PCIE_MEM_BASE #undef CP11X_PCIE0_BASE #undef CP11X_PCIE1_BASE @@ -42,7 +40,6 @@ */ #define CP11X_NAME cp1 #define CP11X_BASE f4000000 -#define CP11X_PCIE_IO_BASE 0xfd000000 #define CP11X_PCIE_MEM_BASE 0xfa000000 #define CP11X_PCIE0_BASE f4600000 #define CP11X_PCIE1_BASE f4620000 @@ -52,7 +49,6 @@ #undef CP11X_NAME #undef CP11X_BASE -#undef CP11X_PCIE_IO_BASE #undef CP11X_PCIE_MEM_BASE #undef CP11X_PCIE0_BASE #undef CP11X_PCIE1_BASE diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi index 3e77cf34604c..7d1ab097453d 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi @@ -10,7 +10,6 @@ #include "armada-common.dtsi" -#define CP11X_PCIEx_IO_BASE(iface) (CP11X_PCIE_IO_BASE + (iface * 0x10000)) #define CP11X_PCIEx_MEM_BASE(iface) (CP11X_PCIE_MEM_BASE + (iface * 0x1000000)) #define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + 0xf00000) @@ -507,11 +506,8 @@ msi-parent = <&gic_v2m0>; bus-range = <0 0xff>; - ranges = - /* downstream I/O */ - <0x81000000 0 CP11X_PCIEx_IO_BASE(0) 0 CP11X_PCIEx_IO_BASE(0) 0 0x10000 /* non-prefetchable memory */ - 0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 0xf00000>; + ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 0xf00000>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; @@ -534,11 +530,8 @@ msi-parent = <&gic_v2m0>; bus-range = <0 0xff>; - ranges = - /* downstream I/O */ - <0x81000000 0 CP11X_PCIEx_IO_BASE(1) 0 CP11X_PCIEx_IO_BASE(1) 0 0x10000 /* non-prefetchable memory */ - 0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 0xf00000>; + ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 0xf00000>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>; interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; @@ -562,11 +555,8 @@ msi-parent = <&gic_v2m0>; bus-range = <0 0xff>; - ranges = - /* downstream I/O */ - <0x81000000 0 CP11X_PCIEx_IO_BASE(2) 0 CP11X_PCIEx_IO_BASE(2) 0 0x10000 /* non-prefetchable memory */ - 0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 0xf00000>; + ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 0xf00000>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-10-04 14:27 UTC|newest] Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-10-04 14:27 [PATCH v2 00/21] Add new Marvell CN9130 SoC support Miquel Raynal 2019-10-04 14:27 ` [PATCH v2 01/21] arm64: dts: marvell: Enumerate the first AP806 syscon Miquel Raynal 2019-10-04 14:27 ` Miquel Raynal 2019-10-04 14:27 ` [PATCH v2 02/21] arm64: dts: marvell: Add AP806-dual missing CPU clocks Miquel Raynal 2019-10-04 14:27 ` Miquel Raynal 2019-10-04 14:27 ` [PATCH v2 03/21] dt-bindings: ap80x: replace AP806 with AP80x Miquel Raynal 2019-10-04 14:27 ` Miquel Raynal 2019-10-04 14:27 ` [PATCH v2 04/21] MAINTAINERS: Add new Marvell CN9130-based files to track Miquel Raynal 2019-10-04 14:27 ` Miquel Raynal 2019-10-04 14:27 ` [PATCH v2 05/21] arm64: dts: marvell: Prepare the introduction of AP807 based SoCs Miquel Raynal 2019-10-04 14:27 ` Miquel Raynal 2019-10-04 14:27 ` [PATCH v2 06/21] arm64: dts: marvell: Move clocks to AP806 specific file Miquel Raynal 2019-10-04 14:27 ` Miquel Raynal 2019-10-04 14:27 ` [PATCH v2 07/21] arm64: dts: marvell: Add support for AP807/AP807-quad Miquel Raynal 2019-10-04 14:27 ` Miquel Raynal 2019-10-04 14:27 ` [PATCH v2 08/21] arm64: dts: marvell: Add AP806-dual cache description Miquel Raynal 2019-10-04 14:27 ` Miquel Raynal 2019-10-04 14:27 ` [PATCH v2 09/21] arm64: dts: marvell: Add AP806-quad " Miquel Raynal 2019-10-04 14:27 ` Miquel Raynal 2019-10-04 14:27 ` [PATCH v2 10/21] arm64: dts: marvell: Add AP807-quad " Miquel Raynal 2019-10-04 14:27 ` Miquel Raynal 2019-10-04 14:27 ` [PATCH v2 11/21] arm64: dts: marvell: Fix CP110 NAND controller node multi-line comment alignment Miquel Raynal 2019-10-04 14:27 ` Miquel Raynal 2019-10-04 14:27 ` [PATCH v2 12/21] arm64: dts: marvell: Prepare the introduction of CP115 Miquel Raynal 2019-10-04 14:27 ` Miquel Raynal 2019-10-04 14:27 ` Miquel Raynal [this message] 2019-10-04 14:27 ` [PATCH v2 13/21] arm64: dts: marvell: Drop PCIe I/O ranges from CP11x file Miquel Raynal 2019-10-04 14:27 ` [PATCH v2 14/21] arm64: dts: marvell: Externalize PCIe macros " Miquel Raynal 2019-10-04 14:27 ` Miquel Raynal 2019-10-04 14:27 ` [PATCH v2 15/21] arm64: dts: marvell: Add support for CP115 Miquel Raynal 2019-10-04 14:27 ` Miquel Raynal 2019-10-04 14:27 ` [PATCH v2 16/21] dt-bindings: marvell: Convert the SoC compatibles description to YAML Miquel Raynal 2019-10-04 14:27 ` Miquel Raynal 2019-10-04 16:13 ` Rob Herring 2019-10-04 16:13 ` Rob Herring 2019-10-04 14:27 ` [PATCH v2 17/21] dt-bindings: marvell: Declare the CN913x SoC compatibles Miquel Raynal 2019-10-04 14:27 ` Miquel Raynal 2019-10-04 16:14 ` Rob Herring 2019-10-04 16:14 ` Rob Herring 2019-10-04 14:27 ` [PATCH v2 18/21] arm64: dts: marvell: Add support for Marvell CN9130 SoC support Miquel Raynal 2019-10-04 14:27 ` Miquel Raynal 2019-10-04 14:27 ` [PATCH v2 19/21] arm64: dts: marvell: Add support for Marvell CN9130-DB Miquel Raynal 2019-10-04 14:27 ` Miquel Raynal 2019-10-04 14:27 ` [PATCH v2 20/21] arm64: dts: marvell: Add support for Marvell CN9131-DB Miquel Raynal 2019-10-04 14:27 ` Miquel Raynal 2019-10-04 14:27 ` [PATCH v2 21/21] arm64: dts: marvell: Add support for Marvell CN9132-DB Miquel Raynal 2019-10-04 14:27 ` Miquel Raynal 2019-10-08 12:25 ` [PATCH v2 00/21] Add new Marvell CN9130 SoC support Gregory CLEMENT 2019-10-08 12:25 ` Gregory CLEMENT
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