From: Sebastian Andrzej Siewior <bigeasy@linutronix.de> To: linux-kernel@vger.kernel.org Cc: tglx@linutronix.de, Russell King <linux@armlinux.org.uk>, linux-arm-kernel@lists.infradead.org, Sebastian Andrzej Siewior <bigeasy@linutronix.de> Subject: [PATCH 01/34] ARM: Use CONFIG_PREEMPTION Date: Tue, 15 Oct 2019 21:17:48 +0200 [thread overview] Message-ID: <20191015191821.11479-2-bigeasy@linutronix.de> (raw) In-Reply-To: <20191015191821.11479-1-bigeasy@linutronix.de> From: Thomas Gleixner <tglx@linutronix.de> CONFIG_PREEMPTION is selected by CONFIG_PREEMPT and by CONFIG_PREEMPT_RT. Both PREEMPT and PREEMPT_RT require the same functionality which today depends on CONFIG_PREEMPT. Switch the entry code, cache over to use CONFIG_PREEMPTION and add output in show_stack() for PREEMPT_RT. Cc: Russell King <linux@armlinux.org.uk> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Thomas Gleixner <tglx@linutronix.de> [bigeasy: +traps.c] Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> --- arch/arm/include/asm/switch_to.h | 2 +- arch/arm/kernel/entry-armv.S | 4 ++-- arch/arm/kernel/traps.c | 2 ++ arch/arm/mm/cache-v7.S | 4 ++-- arch/arm/mm/cache-v7m.S | 4 ++-- 5 files changed, 9 insertions(+), 7 deletions(-) diff --git a/arch/arm/include/asm/switch_to.h b/arch/arm/include/asm/switch_to.h index d3e937dcee4d0..007d8fea71572 100644 --- a/arch/arm/include/asm/switch_to.h +++ b/arch/arm/include/asm/switch_to.h @@ -10,7 +10,7 @@ * to ensure that the maintenance completes in case we migrate to another * CPU. */ -#if defined(CONFIG_PREEMPT) && defined(CONFIG_SMP) && defined(CONFIG_CPU_V7) +#if defined(CONFIG_PREEMPTION) && defined(CONFIG_SMP) && defined(CONFIG_CPU_V7) #define __complete_pending_tlbi() dsb(ish) #else #define __complete_pending_tlbi() diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 858d4e5415326..77f54830554c3 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -211,7 +211,7 @@ ENDPROC(__dabt_svc) svc_entry irq_handler -#ifdef CONFIG_PREEMPT +#ifdef CONFIG_PREEMPTION ldr r8, [tsk, #TI_PREEMPT] @ get preempt count ldr r0, [tsk, #TI_FLAGS] @ get flags teq r8, #0 @ if preempt count != 0 @@ -226,7 +226,7 @@ ENDPROC(__irq_svc) .ltorg -#ifdef CONFIG_PREEMPT +#ifdef CONFIG_PREEMPTION svc_preempt: mov r8, lr 1: bl preempt_schedule_irq @ irq en/disable is done inside diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index c053abd1fb539..abb7dd7e656fd 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -248,6 +248,8 @@ void show_stack(struct task_struct *tsk, unsigned long *sp) #ifdef CONFIG_PREEMPT #define S_PREEMPT " PREEMPT" +#elif defined(CONFIG_PREEMPT_RT) +#define S_PREEMPT " PREEMPT_RT" #else #define S_PREEMPT "" #endif diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 0ee8fc4b4672c..dc8f152f35566 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -135,13 +135,13 @@ ENTRY(v7_flush_dcache_all) and r1, r1, #7 @ mask of the bits for current cache only cmp r1, #2 @ see what cache we have at this level blt skip @ skip if no cache, or just i-cache -#ifdef CONFIG_PREEMPT +#ifdef CONFIG_PREEMPTION save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic #endif mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr isb @ isb to sych the new cssr&csidr mrc p15, 1, r1, c0, c0, 0 @ read the new csidr -#ifdef CONFIG_PREEMPT +#ifdef CONFIG_PREEMPTION restore_irqs_notrace r9 #endif and r2, r1, #7 @ extract the length of the cache lines diff --git a/arch/arm/mm/cache-v7m.S b/arch/arm/mm/cache-v7m.S index a0035c426ce63..1bc3a0a507539 100644 --- a/arch/arm/mm/cache-v7m.S +++ b/arch/arm/mm/cache-v7m.S @@ -183,13 +183,13 @@ ENTRY(v7m_flush_dcache_all) and r1, r1, #7 @ mask of the bits for current cache only cmp r1, #2 @ see what cache we have at this level blt skip @ skip if no cache, or just i-cache -#ifdef CONFIG_PREEMPT +#ifdef CONFIG_PREEMPTION save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic #endif write_csselr r10, r1 @ set current cache level isb @ isb to sych the new cssr&csidr read_ccsidr r1 @ read the new csidr -#ifdef CONFIG_PREEMPT +#ifdef CONFIG_PREEMPTION restore_irqs_notrace r9 #endif and r2, r1, #7 @ extract the length of the cache lines -- 2.23.0
WARNING: multiple messages have this Message-ID (diff)
From: Sebastian Andrzej Siewior <bigeasy@linutronix.de> To: linux-kernel@vger.kernel.org Cc: tglx@linutronix.de, Sebastian Andrzej Siewior <bigeasy@linutronix.de>, Russell King <linux@armlinux.org.uk>, linux-arm-kernel@lists.infradead.org Subject: [PATCH 01/34] ARM: Use CONFIG_PREEMPTION Date: Tue, 15 Oct 2019 21:17:48 +0200 [thread overview] Message-ID: <20191015191821.11479-2-bigeasy@linutronix.de> (raw) In-Reply-To: <20191015191821.11479-1-bigeasy@linutronix.de> From: Thomas Gleixner <tglx@linutronix.de> CONFIG_PREEMPTION is selected by CONFIG_PREEMPT and by CONFIG_PREEMPT_RT. Both PREEMPT and PREEMPT_RT require the same functionality which today depends on CONFIG_PREEMPT. Switch the entry code, cache over to use CONFIG_PREEMPTION and add output in show_stack() for PREEMPT_RT. Cc: Russell King <linux@armlinux.org.uk> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Thomas Gleixner <tglx@linutronix.de> [bigeasy: +traps.c] Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> --- arch/arm/include/asm/switch_to.h | 2 +- arch/arm/kernel/entry-armv.S | 4 ++-- arch/arm/kernel/traps.c | 2 ++ arch/arm/mm/cache-v7.S | 4 ++-- arch/arm/mm/cache-v7m.S | 4 ++-- 5 files changed, 9 insertions(+), 7 deletions(-) diff --git a/arch/arm/include/asm/switch_to.h b/arch/arm/include/asm/switch_to.h index d3e937dcee4d0..007d8fea71572 100644 --- a/arch/arm/include/asm/switch_to.h +++ b/arch/arm/include/asm/switch_to.h @@ -10,7 +10,7 @@ * to ensure that the maintenance completes in case we migrate to another * CPU. */ -#if defined(CONFIG_PREEMPT) && defined(CONFIG_SMP) && defined(CONFIG_CPU_V7) +#if defined(CONFIG_PREEMPTION) && defined(CONFIG_SMP) && defined(CONFIG_CPU_V7) #define __complete_pending_tlbi() dsb(ish) #else #define __complete_pending_tlbi() diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 858d4e5415326..77f54830554c3 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -211,7 +211,7 @@ ENDPROC(__dabt_svc) svc_entry irq_handler -#ifdef CONFIG_PREEMPT +#ifdef CONFIG_PREEMPTION ldr r8, [tsk, #TI_PREEMPT] @ get preempt count ldr r0, [tsk, #TI_FLAGS] @ get flags teq r8, #0 @ if preempt count != 0 @@ -226,7 +226,7 @@ ENDPROC(__irq_svc) .ltorg -#ifdef CONFIG_PREEMPT +#ifdef CONFIG_PREEMPTION svc_preempt: mov r8, lr 1: bl preempt_schedule_irq @ irq en/disable is done inside diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index c053abd1fb539..abb7dd7e656fd 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -248,6 +248,8 @@ void show_stack(struct task_struct *tsk, unsigned long *sp) #ifdef CONFIG_PREEMPT #define S_PREEMPT " PREEMPT" +#elif defined(CONFIG_PREEMPT_RT) +#define S_PREEMPT " PREEMPT_RT" #else #define S_PREEMPT "" #endif diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 0ee8fc4b4672c..dc8f152f35566 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -135,13 +135,13 @@ ENTRY(v7_flush_dcache_all) and r1, r1, #7 @ mask of the bits for current cache only cmp r1, #2 @ see what cache we have at this level blt skip @ skip if no cache, or just i-cache -#ifdef CONFIG_PREEMPT +#ifdef CONFIG_PREEMPTION save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic #endif mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr isb @ isb to sych the new cssr&csidr mrc p15, 1, r1, c0, c0, 0 @ read the new csidr -#ifdef CONFIG_PREEMPT +#ifdef CONFIG_PREEMPTION restore_irqs_notrace r9 #endif and r2, r1, #7 @ extract the length of the cache lines diff --git a/arch/arm/mm/cache-v7m.S b/arch/arm/mm/cache-v7m.S index a0035c426ce63..1bc3a0a507539 100644 --- a/arch/arm/mm/cache-v7m.S +++ b/arch/arm/mm/cache-v7m.S @@ -183,13 +183,13 @@ ENTRY(v7m_flush_dcache_all) and r1, r1, #7 @ mask of the bits for current cache only cmp r1, #2 @ see what cache we have at this level blt skip @ skip if no cache, or just i-cache -#ifdef CONFIG_PREEMPT +#ifdef CONFIG_PREEMPTION save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic #endif write_csselr r10, r1 @ set current cache level isb @ isb to sych the new cssr&csidr read_ccsidr r1 @ read the new csidr -#ifdef CONFIG_PREEMPT +#ifdef CONFIG_PREEMPTION restore_irqs_notrace r9 #endif and r2, r1, #7 @ extract the length of the cache lines -- 2.23.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-10-15 19:21 UTC|newest] Thread overview: 131+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-10-15 19:17 [PATCH 00/34] Treewide: Use CONFIG_PREEMPTION Sebastian Andrzej Siewior 2019-10-15 19:17 ` Sebastian Andrzej Siewior [this message] 2019-10-15 19:17 ` [PATCH 01/34] ARM: " Sebastian Andrzej Siewior 2019-12-08 14:58 ` [tip: sched/urgent] sched/rt, " tip-bot2 for Thomas Gleixner 2019-10-15 19:17 ` [PATCH 02/34] arm64: " Sebastian Andrzej Siewior 2019-10-15 19:17 ` Sebastian Andrzej Siewior 2019-12-08 14:58 ` [tip: sched/urgent] sched/rt, " tip-bot2 for Thomas Gleixner 2019-10-15 19:17 ` [PATCH 03/34] powerpc: " Sebastian Andrzej Siewior 2019-10-15 19:17 ` Sebastian Andrzej Siewior 2019-10-16 4:57 ` Christophe Leroy 2019-10-16 4:57 ` Christophe Leroy 2019-10-16 7:48 ` Sebastian Andrzej Siewior 2019-10-16 7:48 ` Sebastian Andrzej Siewior 2019-10-16 9:33 ` Michael Ellerman 2019-10-16 9:33 ` Michael Ellerman 2019-10-16 9:35 ` Sebastian Andrzej Siewior 2019-10-16 9:35 ` Sebastian Andrzej Siewior 2019-10-24 13:59 ` [PATCH 03/34 v2] " Sebastian Andrzej Siewior 2019-10-24 13:59 ` Sebastian Andrzej Siewior 2019-10-24 16:04 ` [PATCH 03/34 v3] " Sebastian Andrzej Siewior 2019-10-24 16:04 ` Sebastian Andrzej Siewior 2019-11-12 12:38 ` Michael Ellerman 2019-11-12 12:38 ` Michael Ellerman 2019-12-08 14:58 ` [tip: sched/urgent] sched/rt, " tip-bot2 for Thomas Gleixner 2019-12-08 14:58 ` tip-bot2 for Thomas Gleixner 2019-10-15 19:17 ` [PATCH 04/34] ARC: " Sebastian Andrzej Siewior 2019-10-15 19:17 ` Sebastian Andrzej Siewior 2019-12-08 14:58 ` [tip: sched/urgent] sched/rt, " tip-bot2 for Thomas Gleixner 2019-10-15 19:17 ` [PATCH 05/34] c6x: " Sebastian Andrzej Siewior 2019-12-08 14:58 ` [tip: sched/urgent] sched/rt, " tip-bot2 for Thomas Gleixner 2019-10-15 19:17 ` [PATCH 06/34] csky: " Sebastian Andrzej Siewior 2019-10-15 23:29 ` Guo Ren 2019-10-16 7:39 ` Sebastian Andrzej Siewior 2019-10-16 23:31 ` Guo Ren 2019-12-08 14:58 ` [tip: sched/urgent] sched/rt, " tip-bot2 for Thomas Gleixner 2019-10-15 19:17 ` [PATCH 07/34] h8300: " Sebastian Andrzej Siewior 2019-12-08 14:58 ` [tip: sched/urgent] sched/rt, " tip-bot2 for Thomas Gleixner 2019-10-15 19:17 ` [PATCH 08/34] hexagon: " Sebastian Andrzej Siewior 2019-12-08 14:58 ` [tip: sched/urgent] sched/rt, " tip-bot2 for Thomas Gleixner 2019-10-15 19:17 ` [PATCH 09/34] ia64: " Sebastian Andrzej Siewior 2019-10-15 19:17 ` Sebastian Andrzej Siewior 2019-12-08 14:58 ` [tip: sched/urgent] sched/rt, " tip-bot2 for Thomas Gleixner 2019-12-08 14:58 ` tip-bot2 for Thomas Gleixner 2019-10-15 19:17 ` [PATCH 10/34] m68k/coldfire: " Sebastian Andrzej Siewior 2019-10-16 0:50 ` Greg Ungerer 2019-10-16 7:55 ` Sebastian Andrzej Siewior 2019-10-16 12:14 ` Greg Ungerer 2019-10-15 19:17 ` [PATCH 11/34] microblaze: " Sebastian Andrzej Siewior 2019-12-08 14:58 ` [tip: sched/urgent] sched/rt, " tip-bot2 for Thomas Gleixner 2019-10-15 19:17 ` [PATCH 12/34] MIPS: " Sebastian Andrzej Siewior 2019-12-08 14:58 ` [tip: sched/urgent] sched/rt, " tip-bot2 for Thomas Gleixner 2019-10-15 19:18 ` [PATCH 13/34] nds32: " Sebastian Andrzej Siewior 2019-12-08 14:58 ` [tip: sched/urgent] sched/rt, " tip-bot2 for Thomas Gleixner 2019-10-15 19:18 ` [PATCH 14/34] nios2: " Sebastian Andrzej Siewior 2019-12-08 14:58 ` [tip: sched/urgent] sched/rt, " tip-bot2 for Thomas Gleixner 2019-10-15 19:18 ` [PATCH 15/34] parisc: " Sebastian Andrzej Siewior 2019-12-08 14:58 ` [tip: sched/urgent] sched/rt, " tip-bot2 for Thomas Gleixner 2019-10-15 19:18 ` [PATCH 16/34] riscv: " Sebastian Andrzej Siewior 2019-10-15 19:18 ` Sebastian Andrzej Siewior 2019-10-15 20:26 ` Paul Walmsley 2019-10-15 20:26 ` Paul Walmsley 2019-12-08 14:58 ` [tip: sched/urgent] sched/rt, " tip-bot2 for Thomas Gleixner 2019-10-15 19:18 ` [PATCH 17/34] s390: " Sebastian Andrzej Siewior 2019-12-08 14:58 ` [tip: sched/urgent] sched/rt, " tip-bot2 for Thomas Gleixner 2019-10-15 19:18 ` [PATCH 18/34] sh: " Sebastian Andrzej Siewior 2019-10-15 19:18 ` Sebastian Andrzej Siewior 2019-12-08 14:58 ` [tip: sched/urgent] sched/rt, " tip-bot2 for Thomas Gleixner 2019-12-08 14:58 ` tip-bot2 for Thomas Gleixner 2019-10-15 19:18 ` [PATCH 19/34] sparc: " Sebastian Andrzej Siewior 2019-10-15 19:18 ` Sebastian Andrzej Siewior 2019-10-15 20:34 ` David Miller 2019-10-15 20:34 ` David Miller 2019-12-08 14:58 ` [tip: sched/urgent] sched/rt, " tip-bot2 for Thomas Gleixner 2019-12-08 14:58 ` tip-bot2 for Thomas Gleixner 2019-10-15 19:18 ` [PATCH 20/34] xtensa: " Sebastian Andrzej Siewior 2019-10-15 19:43 ` Max Filippov 2019-12-08 14:58 ` [tip: sched/urgent] sched/rt, " tip-bot2 for Thomas Gleixner 2019-10-15 19:18 ` [PATCH 21/34] net: " Sebastian Andrzej Siewior 2019-12-08 14:58 ` [tip: sched/urgent] sched/rt, net: Use CONFIG_PREEMPTION.patch tip-bot2 for Thomas Gleixner 2019-10-15 19:18 ` [PATCH 22/34] xen: Use CONFIG_PREEMPTION Sebastian Andrzej Siewior 2019-10-15 19:18 ` [Xen-devel] " Sebastian Andrzej Siewior 2019-10-16 5:10 ` Jürgen Groß 2019-10-16 5:10 ` [Xen-devel] " Jürgen Groß 2019-12-08 14:58 ` [tip: sched/urgent] sched/rt, " tip-bot2 for Thomas Gleixner 2019-12-08 14:58 ` [Xen-devel] " tip-bot2 for Thomas Gleixner 2019-10-15 19:18 ` [PATCH 23/34] fs: " Sebastian Andrzej Siewior 2019-12-08 14:58 ` [tip: sched/urgent] sched/rt, " tip-bot2 for Thomas Gleixner 2019-10-15 19:18 ` [PATCH 24/34] btrfs: " Sebastian Andrzej Siewior 2019-10-15 20:16 ` David Sterba 2019-12-08 14:58 ` [tip: sched/urgent] sched/rt, " tip-bot2 for Thomas Gleixner 2019-10-15 19:18 ` [PATCH 25/34] mm: " Sebastian Andrzej Siewior 2019-10-16 14:38 ` Christopher Lameter 2019-10-16 14:38 ` Christopher Lameter 2019-12-08 14:58 ` [tip: sched/urgent] sched/rt, " tip-bot2 for Thomas Gleixner 2019-10-15 19:18 ` [PATCH 26/34] Documentation/RCU: Use CONFIG_PREEMPTION where appropriate Sebastian Andrzej Siewior 2019-10-16 4:13 ` Paul E. McKenney 2019-10-16 7:31 ` Sebastian Andrzej Siewior 2019-10-17 3:06 ` Paul E. McKenney 2019-10-15 19:18 ` [PATCH 27/34] rcu: " Sebastian Andrzej Siewior 2019-10-16 4:14 ` Paul E. McKenney 2019-10-15 19:18 ` [PATCH 28/34] drm/i810: Refer to `PREEMPTION' in comment Sebastian Andrzej Siewior 2019-10-16 19:58 ` Daniel Vetter 2019-10-15 19:18 ` [PATCH 29/34] backlight/jornada720: Use CONFIG_PREEMPTION Sebastian Andrzej Siewior 2019-10-15 19:18 ` Sebastian Andrzej Siewior 2019-10-17 11:37 ` Daniel Thompson 2019-10-17 11:37 ` Daniel Thompson 2019-10-17 13:23 ` Lee Jones 2019-10-17 13:23 ` Lee Jones 2019-10-17 13:23 ` Lee Jones 2019-10-17 13:28 ` Sebastian Andrzej Siewior 2019-10-17 13:28 ` Sebastian Andrzej Siewior 2019-10-18 7:38 ` Lee Jones 2019-10-18 7:38 ` Lee Jones 2019-10-18 7:38 ` Lee Jones 2019-10-18 7:40 ` Lee Jones 2019-10-18 7:40 ` Lee Jones 2019-10-18 7:40 ` Lee Jones 2019-10-15 19:18 ` [PATCH 30/34] media: cec-gpio: " Sebastian Andrzej Siewior 2019-10-15 19:53 ` Hans Verkuil 2019-10-16 11:51 ` Hans Verkuil 2019-10-16 12:02 ` Sebastian Andrzej Siewior 2019-10-16 12:24 ` Hans Verkuil 2019-10-15 19:18 ` [PATCH 31/34] locking: " Sebastian Andrzej Siewior 2019-10-16 8:18 ` Peter Zijlstra 2019-12-08 14:58 ` [tip: sched/urgent] sched/rt, " tip-bot2 for Sebastian Andrzej Siewior 2019-10-15 19:18 ` [PATCH 32/34] lib: " Sebastian Andrzej Siewior 2019-12-08 14:58 ` [tip: sched/urgent] sched/core: " tip-bot2 for Sebastian Andrzej Siewior 2019-10-15 19:18 ` [PATCH 33/34] tracing: " Sebastian Andrzej Siewior 2019-10-15 19:24 ` Steven Rostedt 2019-10-15 19:18 ` [PATCH 34/34] workqueue: Use PREEMPTION Sebastian Andrzej Siewior 2019-12-08 14:58 ` [tip: sched/urgent] sched/rt, " tip-bot2 for Sebastian Andrzej Siewior
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