From: Jernej Skrabec <jernej.skrabec@siol.net>
To: mripard@kernel.org, wens@csie.org
Cc: robh+dt@kernel.org, mark.rutland@arm.com, mchehab@kernel.org,
hverkuil@xs4all.nl, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-media@vger.kernel.org,
linux-sunxi@googlegroups.com
Subject: [PATCH v3 3/6] ARM: dts: sunxi: h3/h5: Add MBUS controller node
Date: Wed, 16 Oct 2019 21:28:04 +0200 [thread overview]
Message-ID: <20191016192807.1278987-4-jernej.skrabec@siol.net> (raw)
In-Reply-To: <20191016192807.1278987-1-jernej.skrabec@siol.net>
Both, H3 and H5, contain MBUS, which is the bus used by DMA devices to
access system memory.
MBUS controller is responsible for arbitration between channels based
on set priority and can do some other things as well, like report
bandwidth used. It also maps RAM region to different address than CPU.
Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 107eeafad20a..66bee3bea633 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -109,6 +109,7 @@
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
+ dma-ranges;
ranges;
display_clocks: clock@1000000 {
@@ -544,6 +545,14 @@
};
};
+ mbus: dram-controller@1c62000 {
+ compatible = "allwinner,sun8i-h3-mbus";
+ reg = <0x01c62000 0x1000>;
+ clocks = <&ccu 113>;
+ dma-ranges = <0x00000000 0x40000000 0xc0000000>;
+ #interconnect-cells = <1>;
+ };
+
spi0: spi@1c68000 {
compatible = "allwinner,sun8i-h3-spi";
reg = <0x01c68000 0x1000>;
--
2.23.0
WARNING: multiple messages have this Message-ID (diff)
From: Jernej Skrabec <jernej.skrabec@siol.net>
To: mripard@kernel.org, wens@csie.org
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, hverkuil@xs4all.nl,
linux-sunxi@googlegroups.com, robh+dt@kernel.org,
mchehab@kernel.org, linux-arm-kernel@lists.infradead.org,
linux-media@vger.kernel.org
Subject: [PATCH v3 3/6] ARM: dts: sunxi: h3/h5: Add MBUS controller node
Date: Wed, 16 Oct 2019 21:28:04 +0200 [thread overview]
Message-ID: <20191016192807.1278987-4-jernej.skrabec@siol.net> (raw)
In-Reply-To: <20191016192807.1278987-1-jernej.skrabec@siol.net>
Both, H3 and H5, contain MBUS, which is the bus used by DMA devices to
access system memory.
MBUS controller is responsible for arbitration between channels based
on set priority and can do some other things as well, like report
bandwidth used. It also maps RAM region to different address than CPU.
Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 107eeafad20a..66bee3bea633 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -109,6 +109,7 @@
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
+ dma-ranges;
ranges;
display_clocks: clock@1000000 {
@@ -544,6 +545,14 @@
};
};
+ mbus: dram-controller@1c62000 {
+ compatible = "allwinner,sun8i-h3-mbus";
+ reg = <0x01c62000 0x1000>;
+ clocks = <&ccu 113>;
+ dma-ranges = <0x00000000 0x40000000 0xc0000000>;
+ #interconnect-cells = <1>;
+ };
+
spi0: spi@1c68000 {
compatible = "allwinner,sun8i-h3-spi";
reg = <0x01c68000 0x1000>;
--
2.23.0
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next prev parent reply other threads:[~2019-10-16 19:28 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-16 19:28 [PATCH v3 0/6] media: Introduce Allwinner H3 deinterlace driver Jernej Skrabec
2019-10-16 19:28 ` Jernej Skrabec
2019-10-16 19:28 ` [PATCH v3 1/6] dt-bindings: bus: sunxi: Add H3 MBUS compatible Jernej Skrabec
2019-10-16 19:28 ` Jernej Skrabec
2019-10-16 19:28 ` [PATCH v3 2/6] clk: sunxi-ng: h3: Export MBUS clock Jernej Skrabec
2019-10-16 19:28 ` Jernej Skrabec
2019-10-16 19:28 ` Jernej Skrabec [this message]
2019-10-16 19:28 ` [PATCH v3 3/6] ARM: dts: sunxi: h3/h5: Add MBUS controller node Jernej Skrabec
2019-10-16 19:28 ` [PATCH v3 4/6] dt-bindings: media: Add Allwinner H3 Deinterlace binding Jernej Skrabec
2019-10-16 19:28 ` Jernej Skrabec
2019-10-16 19:28 ` [PATCH v3 5/6] media: sun4i: Add H3 deinterlace driver Jernej Skrabec
2019-10-16 19:28 ` Jernej Skrabec
2019-10-17 7:51 ` Hans Verkuil
2019-10-17 7:51 ` Hans Verkuil
2019-10-17 16:50 ` Jernej Škrabec
2019-10-17 16:50 ` Jernej Škrabec
2019-10-17 9:28 ` Maxime Ripard
2019-10-17 9:28 ` Maxime Ripard
2019-10-17 16:54 ` Jernej Škrabec
2019-10-17 16:54 ` Jernej Škrabec
2019-10-16 19:28 ` [PATCH v3 6/6] dts: arm: sun8i: h3: Enable deinterlace unit Jernej Skrabec
2019-10-16 19:28 ` Jernej Skrabec
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