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From: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
To: a.hajda@samsung.com, narmstrong@baylibre.com,
	Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se,
	jernej.skrabec@siol.net, airlied@linux.ie, daniel@ffwll.ch,
	bjorn.andersson@linaro.org
Cc: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Subject: [PATCH] drm/bridge: ti-sn65dsi86: Decouple DP output lanes from DSI input lanes
Date: Mon, 21 Oct 2019 11:05:32 -0700	[thread overview]
Message-ID: <20191021180532.31210-1-jeffrey.l.hugo@gmail.com> (raw)

Based on work by Bjorn Andersson <bjorn.andersson@linaro.org>

The bridge can be configured to use 1, 2, or 4 DP lanes.  This
configuration is independent of the input DSI lanes.  Right now, the
driver assumes that there is 1:1 mapping of input lanes to output lanes
which is not correct and does not work for manu devices such as the
Lenovo Miix 630 and Lenovo Yoga C630 laptops.

Instead, configure the DP output lanes based on the connection information
to the panel, if available.

Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
---
 drivers/gpu/drm/bridge/ti-sn65dsi86.c | 27 +++++++++++++++++++++++----
 1 file changed, 23 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
index 43abf01ebd4c..1afdc3d5d541 100644
--- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
+++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
@@ -100,6 +100,7 @@ struct ti_sn_bridge {
 	struct drm_panel		*panel;
 	struct gpio_desc		*enable_gpio;
 	struct regulator_bulk_data	supplies[SN_REGULATOR_SUPPLY_NUM];
+	int				dp_lanes;
 };
 
 static const struct regmap_range ti_sn_bridge_volatile_ranges[] = {
@@ -444,7 +445,7 @@ static void ti_sn_bridge_set_dsi_dp_rate(struct ti_sn_bridge *pdata)
 	regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
 
 	/* set DP data rate */
-	dp_rate_mhz = ((bit_rate_mhz / pdata->dsi->lanes) * DP_CLK_FUDGE_NUM) /
+	dp_rate_mhz = ((bit_rate_mhz / pdata->dp_lanes) * DP_CLK_FUDGE_NUM) /
 							DP_CLK_FUDGE_DEN;
 	for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++)
 		if (ti_sn_bridge_dp_rate_lut[i] > dp_rate_mhz)
@@ -504,8 +505,8 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge)
 	regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,
 			   CHA_DSI_LANES_MASK, val);
 
-	/* DP lane config */
-	val = DP_NUM_LANES(pdata->dsi->lanes - 1);
+	/* DP lane config - 4 lanes are encoded with the value "3" */
+	val = DP_NUM_LANES(pdata->dp_lanes == 4 ? 3 : pdata->dp_lanes);
 	regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
 			   val);
 
@@ -699,7 +700,10 @@ static int ti_sn_bridge_probe(struct i2c_client *client,
 			      const struct i2c_device_id *id)
 {
 	struct ti_sn_bridge *pdata;
-	int ret;
+	int ret, len;
+	struct device_node *endpoint;
+	struct property *prop;
+
 
 	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
 		DRM_ERROR("device doesn't support I2C\n");
@@ -727,6 +731,21 @@ static int ti_sn_bridge_probe(struct i2c_client *client,
 		return ret;
 	}
 
+	endpoint = of_graph_get_endpoint_by_regs(pdata->dev->of_node, 1, -1);
+	prop = of_find_property(endpoint, "data-lanes", &len);
+	if (!prop) {
+		DRM_DEBUG("failed to find dp lane mapping, using default\n");
+		pdata->dp_lanes = 1;
+	} else {
+		pdata->dp_lanes = len / sizeof(u32);
+		if (pdata->dp_lanes < 1 || pdata->dp_lanes > 4 ||
+		    pdata->dp_lanes == 3) {
+			DRM_ERROR("bad number of dp lanes: %d\n",
+				  pdata->dp_lanes);
+			return -EINVAL;
+		}
+	}
+
 	dev_set_drvdata(&client->dev, pdata);
 
 	pdata->enable_gpio = devm_gpiod_get(pdata->dev, "enable",
-- 
2.17.1


                 reply	other threads:[~2019-10-21 18:05 UTC|newest]

Thread overview: [no followups] expand[flat|nested]  mbox.gz  Atom feed

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