From: Chris Wilson <chris@chris-wilson.co.uk> To: intel-gfx@lists.freedesktop.org Subject: [PATCH 04/11] drm/i915/gt: Expose engine->mmio_base via sysfs Date: Thu, 24 Oct 2019 12:40:21 +0100 [thread overview] Message-ID: <20191024114028.6170-5-chris@chris-wilson.co.uk> (raw) In-Reply-To: <20191024114028.6170-1-chris@chris-wilson.co.uk> Use the per-engine sysfs directory to let userspace discover the mmio_base of each engine. Prior to recent generations, the user accessible registers on each engine are at a fixed offset relative to each engine -- but require absolute addressing. As the absolute address depends on the actual physical engine, this is not always possible to determine from userspace (for example icl may expose vcs1 or vcs2 as the second vcs engine). Make this easy for userspace to discover by providing the mmio_base in sysfs. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_engine_sysfs.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c index df263af3a9ea..abddd8d0f9ae 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c @@ -48,6 +48,15 @@ inst_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) static struct kobj_attribute inst_attr = __ATTR(instance, 0444, inst_show, NULL); +static ssize_t +mmio_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + return sprintf(buf, "0x%x\n", kobj_to_engine(kobj)->mmio_base); +} + +static struct kobj_attribute mmio_attr = +__ATTR(mmio_base, 0444, mmio_show, NULL); + static const char * const vcs_caps[] = { [ilog2(I915_VIDEO_CLASS_CAPABILITY_HEVC)] = "hevc", [ilog2(I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC)] = "sfc", @@ -170,6 +179,7 @@ void intel_engines_add_sysfs(struct drm_i915_private *i915) &name_attr.attr, &class_attr.attr, &inst_attr.attr, + &mmio_attr.attr, &caps_attr.attr, &all_caps_attr.attr, NULL -- 2.24.0.rc0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
WARNING: multiple messages have this Message-ID (diff)
From: Chris Wilson <chris@chris-wilson.co.uk> To: intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 04/11] drm/i915/gt: Expose engine->mmio_base via sysfs Date: Thu, 24 Oct 2019 12:40:21 +0100 [thread overview] Message-ID: <20191024114028.6170-5-chris@chris-wilson.co.uk> (raw) Message-ID: <20191024114021.8ONvCbGRvwl-Y7wonNSRRokLEoZNF9AQfpBfNDr9hkA@z> (raw) In-Reply-To: <20191024114028.6170-1-chris@chris-wilson.co.uk> Use the per-engine sysfs directory to let userspace discover the mmio_base of each engine. Prior to recent generations, the user accessible registers on each engine are at a fixed offset relative to each engine -- but require absolute addressing. As the absolute address depends on the actual physical engine, this is not always possible to determine from userspace (for example icl may expose vcs1 or vcs2 as the second vcs engine). Make this easy for userspace to discover by providing the mmio_base in sysfs. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_engine_sysfs.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c index df263af3a9ea..abddd8d0f9ae 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c @@ -48,6 +48,15 @@ inst_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) static struct kobj_attribute inst_attr = __ATTR(instance, 0444, inst_show, NULL); +static ssize_t +mmio_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + return sprintf(buf, "0x%x\n", kobj_to_engine(kobj)->mmio_base); +} + +static struct kobj_attribute mmio_attr = +__ATTR(mmio_base, 0444, mmio_show, NULL); + static const char * const vcs_caps[] = { [ilog2(I915_VIDEO_CLASS_CAPABILITY_HEVC)] = "hevc", [ilog2(I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC)] = "sfc", @@ -170,6 +179,7 @@ void intel_engines_add_sysfs(struct drm_i915_private *i915) &name_attr.attr, &class_attr.attr, &inst_attr.attr, + &mmio_attr.attr, &caps_attr.attr, &all_caps_attr.attr, NULL -- 2.24.0.rc0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-10-24 11:40 UTC|newest] Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-10-24 11:40 CI testing of persistence and sysfs Chris Wilson 2019-10-24 11:40 ` [Intel-gfx] " Chris Wilson 2019-10-24 11:40 ` [PATCH 01/11] drm/i915/gem: Make context persistence optional Chris Wilson 2019-10-24 11:40 ` [Intel-gfx] " Chris Wilson 2019-10-25 9:10 ` Joonas Lahtinen 2019-10-25 9:10 ` [Intel-gfx] " Joonas Lahtinen 2019-10-25 18:22 ` Jason Ekstrand 2019-10-25 18:22 ` [Intel-gfx] " Jason Ekstrand 2019-10-25 21:29 ` Chris Wilson 2019-10-25 21:29 ` [Intel-gfx] " Chris Wilson 2019-10-29 16:19 ` Jason Ekstrand 2019-10-29 16:19 ` [Intel-gfx] " Jason Ekstrand 2019-10-29 18:02 ` Chris Wilson 2019-10-29 18:02 ` [Intel-gfx] " Chris Wilson 2019-10-24 11:40 ` [PATCH 02/11] drm/i915: Put future HW and their uAPIs under STAGING & BROKEN Chris Wilson 2019-10-24 11:40 ` [Intel-gfx] " Chris Wilson 2019-10-24 23:25 ` David Airlie 2019-10-24 23:25 ` [Intel-gfx] " David Airlie 2019-10-24 23:35 ` Rodrigo Vivi 2019-10-24 23:35 ` [Intel-gfx] " Rodrigo Vivi 2019-10-25 7:09 ` Jani Nikula 2019-10-25 7:09 ` [Intel-gfx] " Jani Nikula 2019-10-24 11:40 ` [PATCH 03/11] drm/i915/gt: Expose engine properties via sysfs Chris Wilson 2019-10-24 11:40 ` [Intel-gfx] " Chris Wilson 2019-10-24 11:40 ` Chris Wilson [this message] 2019-10-24 11:40 ` [Intel-gfx] [PATCH 04/11] drm/i915/gt: Expose engine->mmio_base " Chris Wilson 2019-10-24 11:40 ` [PATCH 05/11] drm/i915/gt: Expose timeslice duration to sysfs Chris Wilson 2019-10-24 11:40 ` [Intel-gfx] " Chris Wilson 2019-10-24 11:40 ` [PATCH 06/11] drm/i915/gt: Expose reset stop timeout via sysfs Chris Wilson 2019-10-24 11:40 ` [Intel-gfx] " Chris Wilson 2019-10-24 11:40 ` [PATCH 07/11] drm/i915/gt: Expose preempt reset " Chris Wilson 2019-10-24 11:40 ` [Intel-gfx] " Chris Wilson 2019-10-24 11:40 ` [PATCH 08/11] drm/i915/gt: Expose heartbeat interval " Chris Wilson 2019-10-24 11:40 ` [Intel-gfx] " Chris Wilson 2019-10-24 11:40 ` [PATCH 09/11] drm/i915: Flush idle barriers when waiting Chris Wilson 2019-10-24 11:40 ` [Intel-gfx] " Chris Wilson 2019-10-24 11:40 ` [PATCH 10/11] drm/i915: Allow userspace to specify ringsize on construction Chris Wilson 2019-10-24 11:40 ` [Intel-gfx] " Chris Wilson 2019-10-24 11:40 ` [PATCH 11/11] drm/i915/gem: Honour O_NONBLOCK before throttling execbuf submissions Chris Wilson 2019-10-24 11:40 ` [Intel-gfx] " Chris Wilson
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